Communication Apparatus and Decoding Method

ABSTRACT

A communication apparatus includes a storage unit, a row processing unit, and a column processing unit. The row processing unit repeatedly performs row processing to calculate a column-processing LLR for each column and each row in a check matrix. The column processing unit calculates a row-processing LLR for each column and each row of the check matrix, and repeatedly performs column processing to store in the storage unit the minimum value k of absolute values of the row-processing LLR. The row processing unit and the column processing unit alternately performs their processing. The row processing unit performs calculation using an approximate minimum value while the column processing unit cyclically updates the minimum k value of each row.

TECHNICAL FIELD

The present invention relates to an error correction technology indigital communication, and, particularly to a communication apparatus ata receiving side and a decoding method for decoding an LDPC (Low-DensityParity Check)-encoded signal.

BACKGROUND ART

As basic algorithms of decoding an LDPC code, there are a “Sum-Productalgorithm” and a “Min-Sum algorithm”. According to these algorithms, thedecoding is performed while repeatedly calculating a likelihood ratio(LLR) as probabilistic reliability information of a reception signal(see Nonpatent Document 1). The “Sum-Product algorithm” has highdecoding performance, but has high calculation cost for packaging suchas the need for holding a table, because a calculation using amathematical function is required. At least a memory that storesintermediate values by only the number of “1” contained in a binarycheck matrix of “0” and “1” is necessary. On the other hand, the“Min-Sum algorithm” does not require a mathematical function, and hassmall calculation cost, but decoding performance is degraded.

The “Sum-Product algorithm” is explained. First, at the transmitterside, transmission data is LDPC encoded using a parity check matrix H ofM rows×N columns, and a codeword c=(c₁, c₂, . . . , c_(N)) c_(n)=0, 1(n=1, 2, . . . , N). A modulation such as a BPSK (Binary Phase ShiftKeying) modulation is performed to this codeword c, and a modulationsignal x=(x₁, x₂, . . . , x_(N)) is sent.

On the other hand, the receiver side receives, via an Additive WhiteGaussian Noise Channel (AWGN channel), a signal y=(y₁, y₂, . . . ,y_(N)) as expressed by the following Equation (1):

y _(n) =x _(n) +e _(n)  (1)

where e_(n) is a Gaussian noise series of which average is 0, and avariance σ²=N₀/2.

At the receiver side, a predetermined digital demodulation correspondingto the above BPSK modulation is performed to the modulation signalreceived via the above channel. Further, iterative decoding by the“Sum-Product algorithm” is executed to a logarithmic likelihood ratio(LLR) obtained from the demodulation result, and a hard decision resultis finally output.

A conventional decoding method “Sum-Product algorithm” implemented bythe above receiver is shown below.

(Initialization Step)

First, the number of repetitions l=1 and the maximum number ofrepetitions l_(max) are set, and, as LLR: β_(mn) ^((l=1)) from a bitnode to a check node at the initial time, a reception LLR: λ_(n) isinput as given by the following Equation (2):

β_(mn) ⁽¹⁾=λ_(n)

n=1, 2, . . . , N

m=1, 2, . . . , M  (2)

(Row Processing Step)

Next, as row processing, LLR: α_(mn) ⁽¹⁾ at the first repetition(repetition first-time LLR: α_(mn) ⁽¹⁾) of a bit n to be sent from thecheck node m to the bit node n is updated for each m and n by thefollowing Equation (3):

$\begin{matrix}\text{[Expression~~1]} & \; \\{\alpha_{m\; n}^{(1)} = {2\mspace{11mu} {\tanh^{- 1}\left( {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{\tanh\left( \frac{\beta_{{mn}^{\prime}}^{({1 - 1})}}{2} \right)}} \right)}}} & (3)\end{matrix}$

where N(m) is a set of column numbers having “1” of a m-th row, n′ isN(m) other than n, and β_(mn) ^((l−1)) is LLR from the (l−1)-th bit nodeto the check node other than an n-th column.

(Column Processing Step)

Next, as a column processing, a repetition first-time LLR: β_(mn) ⁽¹⁾ ofa bit n to be sent from the bit node n to the check node m is updatedfor each m and n by the following Equation (4):

$\begin{matrix}\text{[Expression~~2]} & \; \\{\beta_{mn}^{(1)} = {\lambda_{n} + {\sum\limits_{m^{\prime} \in {{M{(n)}}\backslash \; m}}\alpha_{m^{\prime}n}^{(1)}}}} & (4)\end{matrix}$

A repetition first-time posterior value β_(n) ⁽¹⁾ of a bit n for a harddecision is updated for each n by the following Equation (5):

$\begin{matrix}\text{[Expression~~3]} & \; \\{\beta_{n}^{(1)} = {\lambda_{n} + {\sum\limits_{m^{\prime} \in {M{(n)}}}\alpha_{n}^{(1)}}}} & (5)\end{matrix}$

where M(n) is a set of row numbers having “1” of an n-th column, m′ isM(n) other than m, and β_(m′n) ⁽¹⁾ is LLR from the first check node tothe bit node other than an m-th row.

(Stop Regulation)

Thereafter, when the repetition first-time posterior value β_(n) ⁽¹⁾ ofthe bit n is “β_(n) ⁽¹⁾>0”, a decoding result is “x_(n)′=1” (where x′corresponds to the original transmission signal x). On the other hand,when “β_(n) ⁽¹⁾≦0”, a decoding result is “x_(n)′=0”, and a decodingresult x′=(x₁′, x₂′, . . . , X_(N)′) is obtained.

When a result of parity check is “Hx′=0” or when the number ofrepetitions is “l=1_(max)” (when any one of these condition issatisfied), a decoding result x′ in this case is output. When none ofthe two conditions is satisfied, “l=l+1” is set, and the process controlreturns to the above row processing. Thereafter, the calculation issequentially performed.

Nonpatent Document 1: Low-Density Parity-Check Codes and Its DecodingAlgorithm, LDPC (Low Density Parity Check) code/sum-product decodingalgorithm, Tadashi Wadayama, Triceps.

DISCLOSURE OF INVENTION Problem to be Solved by the Invention

However, while the above “Sum-Product algorithm” is known to have highdecoding performance, this algorithm requires a repeated calculation(calculation of tan h⁻¹), using a mathematical function. Therefore, thisalgorithm has a problem in that calculation load at the receiver sidebecomes high whether hardware or software is used to realize thisalgorithm. There is also a method of holding a predetermined table todecrease the calculation load (table lookup). However, this methodincreases the memory capacity necessary to store the table.

In the above “Sum-Product algorithm”, at least a memory that storesintermediate values (algorithmic likelihood ratios of each row, updatedvalues for each repetition, etc.) by only the number of “1 (weight)”contained in a binary check matrix of “0” and “1” is necessary. That is,a consumption amount of the memory becomes very large. Further, theabove “Sum-Product algorithm” has also problems that the number ofquantization bits is large, the number of repetitions is large, etc.

The present invention has been achieved to solve the above problems inthe conventional technology and it is an object of the present inventionto provide a communication apparatus and a decoding method, capable ofreducing calculations and a memory capacity required in decoding of anLPDC encoded codeword. The invention also has an object of providing acommunication apparatus and a decoding method, capable of achieving areduction in the quantization size and a reduction in the number ofrepetitions.

Means for Solving Problems

To solve the problems and achieve the object mentioned above, there isprovided a communication apparatus that decodes an LDPC-encoded codewordusing a check matrix including: a retaining unit that retains anintermediate value obtained by a predetermined process in a decodingalgorithm; a row processing unit that performs row processing ofcalculating a logarithmic likelihood ratio (logarithmic likelihood ratioto be sent from a check node to a bit node: column-processing LLR) usedin the column processing based on an absolute value of a logarithmiclikelihood ratio (logarithmic likelihood ratio to be sent from a bitnode to a check node: row-processing LLR) corresponding to a row weightof a check matrix; and a column processing unit that calculates arow-processing LLR to be used in the row processing based on acolumn-processing LLR corresponding to a column weight, and stores aminimum value of absolute values of the row-processing LLR in theretaining unit. The column processing unit performs decoding whileupdating the minimum k value of the row.

EFFECT OF THE INVENTION

According to the present invention, in the LDPC decoding, an absolutevalue of an LLR for row processing is reduced to a minimum k value in arow unit by a cyclic structure. Therefore, there is an effect that thememory capacity required to store the absolute values can besubstantially reduced. Further, according to the present invention,probability propagation can be performed more efficiently than thatperformed by the conventional “Min-Sum algorithm”. Therefore, the numberof repetitions of decoding can be substantially reduced. As a result,the calculations in decoding can be substantially reduced.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a configuration example of a communication system including anLDPC encoder and an LDPC decoder.

FIG. 2 is a configuration example of a row processing unit that executesa row processing step of the “Min-Sum algorithm” in the LDPC decoder.

FIG. 3 is a configuration example of a column processing unit thatperforms a column processing step of the “Min-Sum algorithm” in the LDPCdecoder.

FIG. 4 is a flowchart of a process according to the “Min-Sum algorithm”.

FIG. 5-1 is a configuration example of an LDPC decoder according to afirst embodiment.

FIG. 5-2 is a configuration example of the LDPC decoder according to thefirst embodiment.

FIG. 6 is a configuration example of a row processing unit that performsrow processing according to the “Cyclic approximated min algorithm”.

FIG. 7-1 is a configuration example of a column processing unit thatperforms column processing according to the “Cyclic approximated minalgorithm”.

FIG. 7-2 is a configuration example of the column processing unit thatperforms column processing according to the “Cyclic approximated minalgorithm”.

FIG. 8 is a schematic diagram for explaining column processing of n=15when information of n=15 is held in a Min 2LLR.

FIG. 9 is a flowchart of a process according to the “Cyclic approximatedmin algorithm”.

FIG. 10 is an example of column number notation.

FIG. 11 is a graph of results of a comparison simulation between the“Cyclic approximated min algorithm” and the “Min-Sum algorithm”.

FIG. 12 is a graph of results of a comparison simulation between the“Cyclic approximated min algorithm” and the “Min-Sum algorithm”.

FIG. 13 is a configuration example of an LDPC decoder according to asecond embodiment.

FIG. 14 is a graph of performance comparison regarding the number ofrepetitions.

FIG. 15 is a configuration example of a row processing unit thatperforms row processing according to a third embodiment.

FIG. 16 is a configuration example of a row processing unit thatperforms row processing according to a fourth embodiment.

FIG. 17 is a graph of results of comparison between a decoding algorithmusing the “Cyclic approximated min algorithm” or the “Overlapped cyclicapproximated min algorithm” applied to the “δ min algorithm”, and the“Sum-Product algorithm”.

FIG. 18 is a configuration example of a row processing unit thatperforms row processing according to a fifth embodiment.

FIG. 19 is a configuration example of a column processing unit thatperforms column processing in the “Serial cyclic approximated minalgorithm” according to a sixth embodiment.

EXPLANATIONS OF LETTERS OR NUMERALS

-   1 LDPC encoder-   2 Modulator-   3 Communication channel-   4 Demodulator-   5 LDPC decoder-   11 Reception-LLR calculating unit-   12 Decoding core unit-   21, 21 a Decoding core unit-   22, 22-1, 22-2, 22-G Row processing unit-   23, 23-1, 23-2, 23-G Column processing unit-   24 Decoding-result determining unit-   25, 25 a Controller-   31, 31 a, 31 b, 31 c Minimum-value selecting unit-   32 Sign calculating unit-   33 LLR calculating unit-   41 α adding unit-   42 λ adding unit-   43 Minimum-k-value comparing unit-   44 Sign calculating unit-   45 Switch

BEST MODE(S) FOR CARRYING OUT THE INVENTION

Exemplary embodiments of a communication apparatus and a decoding methodaccording to the present invention are explained in detail below withreference to the accompanying drawings. Note that the present inventionis not limited to the embodiments. The present invention can be appliedto decoding at a terminal and a base station, in wireless communicationthrough, for example, a portable telephone. The present invention canalso be applied to decoding in satellite communication, an HDD, opticalcommunication, a wireless LAN, a quantum code, and the like.

First Embodiment

Described first is positioning, in a communication system, of acommunication apparatus and an LDPC decoder that implements a decodingmethod according to the present invention. FIG. 1 is a configurationexample of the communication system including an LDPC encoder and anLDPC decoder. In FIG. 1, a communication apparatus at the transmissionside (hereinafter, “transmitting device”) includes an LDPC encoder 1 anda modulator 2, and a communication apparatus at the receiving side(hereinafter, “receiving device”) includes a demodulator 4 and an LDPCdecoder 5.

A flow of encoding and decoding in the communication system that employsan LDPC code is briefly explained. The LDPC encoder 1 within thetransmitting device generates a generation matrix G of K rows×N columnsaccording to a known method (K: an information length, N: a codewordlength). The LDPC encoder 1 receives a message (m₁, m₂, . . . , m_(K))of the information length K, and generates a codeword C, using thismessage and the above generated matrix G, as represented by thefollowing Equation (6):

$\begin{matrix}\begin{matrix}{C = {\left( {m_{1},m_{2},\ldots \mspace{14mu},m_{K}} \right)G}} \\{= \left( {c_{1},c_{2},\ldots \mspace{14mu},c_{N}} \right)}\end{matrix} & (6)\end{matrix}$

When a parity check matrix for the LDPC is H (M rows×N columns), thegeneration matrix G satisfies GH^(T)=0 (T is a transposed matrix), H(c₁, c₂, . . . , c_(N)) T=0.

The modulator 2 performs a digital modulation to the codeword Cgenerated by the LDPC encoder 1, by a predetermined modulation systemsuch as BPSK, multivalue PSK, multivalue QAM, etc., and transmits amodulation signal x=(x₁, x₂, . . . , x_(N)) to the receiving device viaa communication channel 3.

On the other hand, in the receiving device, the demodulator 4 performs adigital demodulation corresponding to the above modulation system suchas BPSK, multivalue PSK, multivalue QAM, etc. to a modulation signaly=(y₁, y₂, y_(N)) that is received via the communication channel 3.Further, the LDPC decoder 5 performs decoding according to the decodingalgorithm of the present embodiment, described later, using alogarithmic likelihood ratio (LLR) obtained from the demodulationresult, and outputs a hard decision value (corresponding to the originalmessage m₁, m₂, m_(K)) as a decoding result.

Before explaining the decoding algorithm of the present embodiment, the“Min-Sum algorithm” is explained as the conventional decoding algorithmthat is the basis of the decoding algorithm.

According to the “Min-Sum algorithm”, the initialization step similar tothat of the “Sum-Product algorithm” described above is first performed.Next, the row processing step of the “Min-Sum algorithm” is performed.Thereafter, the column processing step and the stop regulation similarto those of the “Sum-Product algorithm” described above are performed tocalculate and update probability information.

FIG. 2 is a configuration example of a row processing unit that performsa row processing step of the “Min-Sum algorithm” in an LDPC decoder.This row processing unit includes: a minimum-value selecting unit 101including a memory unit 111 that stores therein the LLR: β_(mn′)^((l=1)) of a row weight portion of the parity check matrix H, and acomparator 112 that compares sizes of the LLR and outputs a minimumvalue of the LLR; a sign calculating unit 102 including a memory unit113 that stores therein a sign of an LLR of the row weight portion, anda multiplying unit 114 that multiplies signs of the LLR (+ or −); and anLLR calculating unit 103 that calculates an LLR: α_(mn) ⁽¹⁾ bymultiplying a minimum value obtained from the minimum-value selectingunit 101 with a multiplication result of signs (+ or −) obtained fromthe sign calculating unit 102.

In the row processing unit, the comparator 112 of the minimum-valueselecting unit 101 includes a plurality of comparators of two inputs (a,b). Each comparator receives LLR for comparison from the above memoryunit 111 and a former-stage comparator (the first-stage comparatorreceives LLR from only the memory unit 111), and when “|a|<|b|”, eachcomparator outputs |a|. In other cases, each comparator outputs |b|,thereby outputting a minimum value of absolute values of the LLR. TheLLR calculating unit 103 multiplies the above minimum value with themultiplication result of the above sign, and delivers the LLR: α_(mn)⁽¹⁾ as the multiplication result, to the column processing unit.

FIG. 3 is a configuration example of the column processing unit thatperforms a column processing step of the “Min-Sum algorithm” in an LDPCdecoder. This column processing unit retains the LLR: αm′n⁽¹⁾ of acolumn weight of the parity check matrix H, and adds each LLR, therebyoutputting the repetition first-time posterior value β_(n) ⁽¹⁾.

(Row Processing Step)

The row processing of the above “Min-Sum algorithm” can be generalizedby the following Equation (7). In this case, as the row processing, therepetition first-time LLR: α_(mn) ⁽¹⁾ of the bit n from the check node mto the bit node n is updated for each of m and n by the followingEquation (7):

$\begin{matrix}\text{[Expression~~4]} & \; \\\begin{matrix}{\alpha_{mn}^{(1)} = {2\mspace{11mu} {\tanh^{- 1}\left( {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{\tanh\left( \frac{\beta_{{mn}^{\prime}}^{({1 - 1})}}{2} \right)}} \right)}}} \\{= {2\mspace{11mu} {\tanh^{- 1}\left( {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({1 - 1})} \right)} \cdot {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{\tanh\left( \frac{\beta_{{mn}^{\prime}}^{({1 - 1})}}{2} \right)}}}} \right)}}} \\{= {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{{{{sgn}\left( \beta_{{mn}^{\prime}}^{({1 - 1})} \right)} \cdot 2}\mspace{11mu} {\tanh^{- 1}\left( {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{\tanh\left( \frac{\beta_{{mn}^{\prime}}^{({1 - 1})}}{2} \right)}} \right)}}}} \\{\approx {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({1 - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{\beta_{{mn}^{\prime}}^{({1 - 1})}}}}}}\end{matrix} & (7)\end{matrix}$

where min |β_(mn′) ^((l−1))| is the minimum value of absolute values ofthe LLR: β_(mn′) ^((l−1)) excluding the n-th column in the m-th row ofthe parity check matrix H, and sgn (β_(mn′) ^((l−1))) is the sign of theLLR: β_(mn′) ^((l−1)) excluding the n-th column.

As described above, according to the “Min-Sum algorithm”, after a rowprocessing step, processing based on column processing and stopregulation similar to those of the “Sum-Product algorithm” is performedto obtain a final sign result.

Next, the flow of the process according to the “Min-Sum algorithm” isbriefly explained referring to FIG. 4.

According to the “Min-Sum algorithm”, a reception LLR is calculated fromreception information (steps S1, S2), and the calculation result is setin the memory unit 111 as an initial value. Further, the number ofrepetitions is initialized as l=1 (step S3). Row processing is performedfirst time in the iterative decoding calculation (repetition first-timedecoding calculation) (step S4: the first iterative decoding to the lastiterative decoding). Next, column processing in the repetitionfirst-time decoding calculation is performed, and thereafter, aposterior value calculated in the repetition first-time decodingcalculation is subjected to a hard decision. This determination value isdetermined as a decoding result, and a parity check is performed (stopregulation). In the above stop regulation, when the parity check resultbecomes OK or when the number of repetitions becomes l=1_(max), adecoding result this time is finally output (step S5).

In the above “Min-Sum algorithm”, calculations and the required memorycapacity are reduced from those of the “Sum-Product algorithm”, byapproximating the row processing of the “Sum-Product algorithm”, i.e.,Equation (3). However, in the above “Min-Sum algorithm”, a large memorycapacity corresponding to the number of “1 (weight)” contained in theparity check matrix H is necessary to store the intermediate value.Further improvement is necessary to reduce the required memory capacity.

The decoding algorithm according to the present embodiment explainedbelow achieves a further reduction in required memory capacity andcalculations, and is the improved algorithm of the “Min-Sum algorithm”as the approximated decoding method of the “Sum-Product algorithm”, forexample.

A configuration of the LDPC decoder 5 constituting the receiving deviceaccording to the present invention, and a decoding method (decodingalgorithm) performed by the LDPC decoder 5, are explained in detailbelow with reference to the drawings.

FIG. 5-1 depicts a configuration of the LDPC decoder 5 according to thepresent embodiment. This LDPC decoder 5 includes a reception-LLRcalculating unit 11 that calculates the reception LLR from the receptioninformation, and the decoding core unit 12 that performs decodingaccording to the present embodiment. The decoding core unit 12 includesan intermediate-result retaining unit 21 configured by a memory whichstores therein an intermediate result (intermediate value) of decoding,a row processing unit 22 that performs row processing according to thepresent embodiment, a column processing unit 23 that performs columnprocessing according to the present embodiment, a decoding-resultdetermining unit 24 that performs a hard decision on a posterior valuein the column processing and an error determination of a parity checkresult, as a stop regulation according to the present embodiment, and acontroller 25 that performs a repetition control of decoding.

The decoding algorithm according to the present embodiment is a methodof cyclically updating only the absolute value of the LLR of the minimumk value. Because this algorithm is the method of decoding using anapproximate minimum value instead of an accurately minimum value, thismethod is hereinafter called the “Cyclic approximated min algorithm”.The minimum k value represents “from the minimum value to the k-th valuein the ascending order.

The “Cyclic approximated min algorithm” executed in the receiving deviceis shown below.

(Initialization Step)

First, the number of repetitions l=1 and the maximum number ofrepetitions l_(max) are set. The LLR of the minimum k value of the m-throw at the initial time is set as β_(mn(i)) ⁽⁰⁾, and a reception LLR:λ_(n) is input to obtain B_(mn(i)) as in the following Equation (8). Asa sign of the LLR: β_(mn) ⁽⁰⁾ of the m-th row at the initial time,sgn(λ_(n)) is input to obtain S_(m) as in the following Equation (8):

$\begin{matrix}\text{[Expression~~5]} & \; \\{{{B_{{mn}{(i)}} = {{\beta_{{mn}{(i)}}^{(0)}} = {\min\limits_{n \in {{N{(m)}}\backslash \; {\{{{n{(1)}},\; {n{(2)}},\; \ldots \;,\; {n{({i - 1})}}}\}}}}\left\lbrack {\lambda_{n}} \right\rbrack}}},{\forall{i \in \left\lbrack {1,k} \right\rbrack}}}{S_{m} = {\prod\limits_{n \in {N{(m)}}}{{sgn}\left( \lambda_{n} \right)}}}{{n(i)} = {\arg \; {\min\limits_{n \in {{N{(m)}}\backslash \; {\{{{n{(1)}},\; {n{(2)}},\; \ldots \;,\; {m{({1 - 1})}}}\}}}}\left\lbrack {\lambda_{n}} \right\rbrack}}}{{n(0)} = \varphi}} & (8)\end{matrix}$

where B_(mn(i)) is an absolute value of the LLR: β_(mn(i)) of theminimum k value of the m-th row, n(i) is a column number of the minimumi-th LLR in B_(mn(i)), and S_(m) is a product of signs (+ or −) of theLLR: β_(mn) of the m-th row.

(Row Processing Step)

In the present embodiment, a starting column of the row processing isarbitrary. At the stage where the process ends to the last column,decoding is performed again cyclically from the first column. As the rowprocessing, the repetition first-time LLR: α_(mn) ⁽¹⁾ of the bit n to besent from the check node m to the bit node n is updated for 1≦n≦N andfor each m by the following Equation (9):

$\begin{matrix}\text{[Expression~~6]} & \; \\{\begin{matrix}{\alpha_{mn}^{(1)} = {\prod\limits_{\underset{n^{\prime} < n}{n^{\prime} \in {{N{(m)}}\backslash \; n}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(1)} \right)} \cdot {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({1 - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({1 - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}\end{matrix}{S_{m}^{\prime} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({1 - 1})} \right)}}}} & (9)\end{matrix}$

where N_(k)(m) is the set of n(i) of the m-th row, and is expressed asN_(k)(m)={n(1), n(2), . . . , n(k)}. Specifically, when the currentcolumn number is n, a column number that satisfies “n′<n” takes theproduct of signs of the LLR: β_(mn′) ⁽¹⁾ updated in the first-timecolumn processing, and a column number that satisfies “n′>n” takes theproduct of signs of the LLR: β_(mn′) ^((l−1)) updated by the (l−1)-thtime column processing. A result of multiplying these results by theminimum LLR: min [β_(mn′)] in the minimum k value of the m-th row is setas the updated LLR: α_(mn) ⁽¹⁾ of the column number n. In the presentembodiment, the term of multiplying the product of the signs of β_(mn′)⁽¹⁾ by the product of the signs of β_(mn′) ^((l−1)) is substituted bythe term of multiplying S_(m) updated at the (l−1)-th time by the signof β_(mn′) updated at the (l−1)-th time. With this arrangement,calculations and the required memory capacity can be reduced.

(Column Processing Step)

Next, as the column processing, the repetition first-time LLR: β_(mn)⁽¹⁾ of the bit n to be sent from the bit node n to the check node m isupdated for each m and n by the following Equation (10):

$\begin{matrix}\text{[Expression~~7]} & \; \\{{\beta_{mn}^{(1)} = {\lambda_{n} + {\sum\limits_{m^{\prime} \in {{M{(n)}}\backslash \; m}}\alpha_{m^{\prime}n}^{(1)}}}}{S_{m} = {S_{m}^{\prime} \cdot {{sgn}\left( \beta_{mn}^{(1)} \right)}}}{{n(i)} = {\arg \; {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; {\{{{n{(1)}},\; {n{(2)}},\; \ldots \;,\; {n{({i - 1})}},\; {n{(i)}}}\}}}}\left\lbrack {B_{{mn}^{\prime}},{\beta_{mn}^{(1)}}} \right\rbrack}}}{{B_{{mn}_{(i)}} = {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; {\{{{n{(1)}},\; {n{(2)}},\; \ldots \;,\; {n{({i - 1})}},\; {n{(i)}}}\}}}}\left\lbrack {B_{{mn}^{\prime}},{\beta_{mn}^{(1)}}} \right\rbrack}},{\forall{i \in \left\lbrack {1,k} \right\rbrack}}}} & (10)\end{matrix}$

Specifically, in the column number n, a result of the addition of thereception LLR: λ_(n), and a total value of the LLR: α_(m′n) ⁽¹⁾ otherthan the m-th row LLR updated in the first-time row processing isexpressed as the updated LLR: β_(mn′) ⁽¹⁾. The above S_(m)′ ismultiplied by the sign (+ or −) of β_(mn) ⁽¹⁾ updated in the first-timecolumn processing, thereby updating S_(m) to be used in the rowprocessing. The two equations in Equation (10) prescribe the sortprocess (minimum k value) of β_(mn(1)).

To perform a hard decision for each n, the repetition first-timeposterior value β_(n) ⁽¹⁾ of the bit n is updated by the followingEquation (11);

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 8} \right\rbrack & \; \\{\beta_{n}^{(1)} = {\lambda_{n} + {\sum\limits_{m^{\prime} \in {M{(n)}}}\alpha_{n}^{(1)}}}} & (11)\end{matrix}$

(Stop Regulation)

Thereafter, when the repetition first-time posterior value β_(n) ⁽¹⁾ ofthe bit n is “βn⁽¹⁾>0”, for example, a decoding result is “x_(n)′=1”(where x′ corresponds to the original transmission signal x). On theother hand, when “β_(n) ⁽¹⁾≦0”, a decoding result is “x_(n)′=0”, and adecoding result x′=(x₁′, x₂′, . . . , x_(N)′) is obtained.

When the result of parity check is “Hx′=0” or when the number ofrepetitions is “l==1_(max)” (when any one of these condition issatisfied), a decoding result x′ in this case is output. When none ofthe two conditions is satisfied, “l=l+1” is set, and the process controlreturns to the above row processing. Thereafter, the calculation issequentially performed.

A characteristic operation of the LDPC decoder 5 that performs the above“Cyclic approximated min algorithm” is explained in detail withreference to a configuration diagram.

FIG. 6 is a configuration example of the row processing unit 22 thatperforms row processing according to the “Cyclic approximated minalgorithm”. The row processing unit 22 includes a minimum-valueselecting unit 31, a sign calculating unit 32, and an LLR calculatingunit 33. In FIG. 6, a Min 1LLR (minimum LLR of the m-th row) isB_(mn(1)), a Min 2LLR (second minimum LLR of the m-th row) is B_(mn(2)),and these are the values retained in the intermediate-result retainingunit 21. In FIG. 6, S_(m) and the “sign of the LLR: β_(mn) of the m-throw and n-th column of the (l−1)-th time” are also the values retainedin the intermediate-result retaining unit 21.

The minimum-value selecting unit 31 selects the Min 2LLR(B_(mn(2))) whenthe column number n to be row-processed coincides with the column numbern(1) of the Min 1LLR(B_(mn(1))), and selects the Min 1LLR(B_(mn(1))) inother cases, and outputs the selected result. The sign calculating unit32 multiplies the “S_(m) updated by the (l−1)-th time column processing”by the “sign of the LLR: β_(mn) of the m-th row and n-th column of the(l−1)-th time”, and outputs S_(m)′ as a result of the multiplication. Inthis case, S_(m)′ is retained in the intermediate-result retaining unit21. The LLR calculating unit 33 multiplies the minimum LLR obtained fromthe minimum-value selecting unit 31 by the multiplication result S_(m)′of the sign (+ or −) obtained from the sign calculating unit 32, therebycalculating LLR: α_(mn) ⁽¹⁾. Based on this, according to the “Min-Sumalgorithm”, the memory that has been necessary by the row weight portioncan be reduced to the k value portion.

FIG. 7-1 is a configuration example of the column processing unit 23that performs column processing according to the “Cyclic approximatedmin algorithm”. This column processing unit 23 includes an α adding unit41, a λ adding unit 42, a minimum-k-value comparing unit 43, and a signcalculating unit 44. In the present embodiment, k=3 is described as anexample. In FIG. 7-1, LLR of a column weight portion, α_(mn), λ_(n),S_(m)′, Min 1LLR, Min 2LLR, Min 3LLR (the third-minimum LLR of the m-throw) are the values retained in the intermediate-result retaining unit21.

In the column processing unit 23, the α adding unit 41 adds all LLR:α_(m′n) ⁽¹⁾ other than those of the m-th row LLR updated in thefirst-time row processing. Further, the λ adding unit 42 adds thereception LLR: λ_(n) to the result of the addition by the α adding unit41, and outputs β_(mn) ⁽¹⁾. The minimum-k-value comparing unit 43 (k=3)receives |β_(mn) ⁽¹⁾|. Although not shown in FIG. 7-1, when n of then-th column to be column processed coincides with any one of n(1), n(2),n(3) indicating the column numbers corresponding to B_(mn(1)),B_(mn(2)), B_(mn(3)), held in the Min 1LLR, Min 2LLR, Min 3LLRrespectively, for example, B_(mn(i)) of n=n(i) is thinned, and theoperation as shown in FIG. 8 is performed. Specifically, informationheld in the Min 2LLR is deleted, and information held in the Min 3LLR isshifted to the Min 2LLR. A maximum value “FFFF”, for example (in thecase of 16 bits), is stored in the Min 3LLR. Accordingly, a comparisonprocess excluding the column to be processed can be performed, and atleast the Min 3LLR can be necessarily updated by the column processing.After that, as shown in FIG. 7-1, |_(mn) ⁽¹⁾| is compared with each ofthe Min 1LLR, Min 2LLR, Min 3LLR. When “|β_(mn) ⁽¹⁾|<Min 3LLR”, the LLRof the minimum 3 value is updated. On the other hand, the sign of β_(mn)⁽¹⁾ output by the λ adding unit 42 is retained in theintermediate-result retaining unit 21, as the “sign of the LLR: β_(mn)⁽¹⁾ of the m-th row and n-th column of the first time”. Further, thesign calculating unit 44 multiplies S_(m)′ updated in the first-time rowprocessing, by the sign of the above β_(mn) ⁽¹⁾, and updates S_(m)retained in the intermediate-result retaining unit 21, using a result ofthis multiplication. In comparing |β_(mn) ⁽¹⁾| with each of the Min1LLR, Min 2LLR, Min 3LLR, |β_(mn) ⁽¹⁾| is first compared with the Min2LLR as the center value of B_(mn(i)), and thereafter, comparison isperformed in a tree shape as shown in FIG. 7-1. For example, there is aneffect that the execution time becomes {(k+1)/2}/2 (where k is an oddnumber), as compared with the effect when |β_(mn) ⁽¹⁾| is compared firstwith the Min 1LLR that becomes the minimum value. When k is an evennumber, there are two center values of B_(mn(i)). In this case, any oneof the two values can be compared first. When k is an even number, thereis an effect that the execution time becomes {k/2+1}/k (where k is aneven number), as compared with the effect when |βmn⁽¹⁾| is comparedfirst with the Min 1LLR that becomes the minimum value.

The same process as described above can also be achieved with theconfiguration shown in FIG. 7-2. In this case, the α adding unit 41performs only the addition of all the LLR of the column weight portion,and thereafter, the λ adding unit 42 adds λ_(n), outputs a result of theaddition to the decoding-result determining unit 24, and subtractsα_(mn) as the LLR of the m-th row. In this procedure, the same result asobtained in the above process can also be obtained. In this case, theconfiguration of the LDPC encoder becomes as shown in FIG. 5-2.

The flow of the process in the “Cyclic approximated min algorithm”according to the present embodiment is explained with reference to FIG.9.

According to the “Cyclic approximated min algorithm”, the reception-LLRcalculating unit 11 calculates the reception LLR from the receptioninformation (steps S11, S12), and sets a result of the calculation tothe intermediate-result retaining unit 21, as an initial value (stepS13). The controller 25 initializes the number of repetitions as l=1(step S13). The calculation of Equation (8) is cyclically performed fromn=1 to n=N, using the λ adding unit 42, the minimum-k-value comparingunit 43, and the sign calculating unit 44, out of the column processingunit 23 (step S13).

Next, the decoding core unit 12 performs the first-time (first-time tothe last-time) iterative decoding calculation (step S14). Specifically,as the first-time iterative decoding, the row processing unit 22performs the row processing (using the reception LLR) to the row having“1” in the first column, and delivers a result of the calculation to thecolumn processing unit 23. Thereafter, the column processing unit 23performs the column processing of the first column, and retains(updates) B_(mn(i)) and S_(m), as a result of the calculation, in theintermediate-result retaining unit 21. Thereafter, processing similar tothe above is performed in the order of the second column, third column,. . . , N-th column, and B_(mn(i)) and S_(m) are retained each time inthe intermediate-result retaining unit 21 (corresponding to theiterative decoding first time). At the second and subsequent iterativedecoding, the row processing is performed using the LLR and S_(m)updated in the processing one before. In other cases, decoding isperformed as in the first time.

After executing the first-time iterative decoding, the decoding-resultdetermining unit 24 performs a hard decision on the posterior valuecalculated at the repetition first time, determines this determinationvalue as the decoding result x′, and performs a parity check (stopregulation). In the stop regulation, when a result of the parity checkis OK (“Hx′=0”) or when the number of repetitions is l=1_(max), thedecoding result x′ at this time is finally output (step S15). When theabove two conditions are not satisfied, the controller 25 sets l=l+1,and the decoding core unit 12 performs the (l+1)-th time iterativedecoding.

Deletion of the memory size according to a notation method of a columnnumber is explained next. FIG. 10 depicts a column number notationaccording to the present embodiment. In the “Cyclic approximated minalgorithm”, column numbers are noted in the ascending order from n=0,for example. Conventionally, a column number n is expressed as thecolumn number itself (absolute column number) of the parity checkmatrix. However, in the present embodiment, column numbers are expressedas relative column numbers, such as a minimum column number of “1” ofthe m-th row in the parity check matrix is expressed as n=0, a columnnumber of the next “1” of the m-th row is expressed as n=1, andthereafter, the column numbers are expressed as n=2, 3, . . . , at each“1”. That is, conventionally, when the absolute column number of “1” inthe parity check matrix is “32768”, the number of bits necessary toexpress the column number is 15 bits. On the other hand, according tothe present embodiment, when the row weight is eight, the memory sizecan be reduced to three bits which can express 0 to 7. When the rowweight is 16, the memory size can be reduced to four bits which canexpress 0 to 15.

As described above, according to the present embodiment, the LDPCdecoding is performed to minimize the absolute value |β_(mn)| of the LLRfor the row processing, to the minimum k value in row unit by the cyclicstructure. Therefore, the memory capacity required to store the absolutevalues can be substantially reduced. When the row weight is 20 and alsok=3, for example, the required memory capacity can be reduced to 3/20 ofthe conventional capacity. Further, by changing the column number fromthe absolute column number (1, 3, 10, 15 . . . ) to the relative columnnumber (0, 1, 2, 3 . . . ), the required memory capacity can be furtherreduced.

In the “Cyclic approximated min algorithm” according to the presentembodiment, calculation and updating of probability information (LLR) bythe row processing and column processing are performed cyclically foreach one bit. Accordingly, probability propagation can be performed moreefficiently than that according to the conventional “Min-Sum algorithm”.

For example, FIG. 11 and FIG. 12 depict results of a comparisonsimulation between the “Cyclic approximated min algorithm” and the“Min-Sum algorithm”. An LDPC code has a maximum row weight of 8 in theirregular EG code. In FIG. 11, the number of decoding iterations isfixed to 100 times, and the number of minimum values stored in the“Cyclic approximated min algorithm” is changed to 3, 4, 5, and theperformance is compared with that of the “Cyclic approximated minalgorithm”. In FIG. 11, CyclicX min is the “Cyclic approximated minalgorithm” holding the minimum X value, and Min-Sum is the “Min-Sumalgorithm”. As is clear from FIG. 11, it can be confirmed that decodingperformance is not degraded while decreasing the memory, by the “Cyclicapproximated min algorithm” according to the present embodiment.

FIG. 12 depicts a result of comparing the average number of repetitionsrequired until decoding succeeds, in the “Cyclic approximated minalgorithm” and the “Min-Sum algorithm”. In FIG. 12, CyclicX min is the“Cyclic approximated min algorithm” holding the minimum X value, andMin-Sum is the “Min-Sum algorithm”. As is clear from this result,probability propagation is performed efficiently in the “Cyclicapproximated min algorithm”, and the decoding number of repetitions canbe substantially reduced. That is, according to the present embodiment,the calculations in decoding can be substantially reduced by the “Cyclicapproximated min algorithm”.

While, in the present embodiment, the LLR to be row processed has onevalue, the k number can be any number equal to or higher than twovalues. The present embodiment explains, by way of example and withoutlimitation, that the row processing and the column processing areperformed one time alternately, and the updating of the probabilityinformation (LLR) by the row processing and the column processing iscyclically performed each one bit. Alternatively, after the rowprocessing is performed a plurality of times, the column processing canbe performed by a plurality of times. That is, calculation and updatingof probability information (LLR) by the row processing and the columnprocessing can be performed cyclically for a plurality of bits eachtime.

Second Embodiment

A receiving device and a decoding method according to a secondembodiment are explained next. LDPC decoding according to the presentembodiment can be applied when the calculation and updating of theprobability information (LLR) by the row processing and columnprocessing are performed for each one bit or a predetermined pluralityof bits. For example, the number of repetitions can be reduced byparallelizing calculations. In the present embodiment, the “Cyclicapproximated min algorithm” is executed using what is called“Overlapped” B_(mn) ^(C) and S_(m), by arranging such that the B_(mn(i))and S_(m) of the intermediate-result retaining unit are one setregardless of the number of parallelization, and parallelized allprocessing units update the same B_(mn) ^(C) and S_(m). The decodingalgorithm according to the present embodiment is hereinafter called the“Overlapped cyclic approximated min algorithm”.

The “Overlapped cyclic approximated min algorithm” executed by thereceiving device according to the present embodiment is shown below.

(Initialization Step)

First, the number of repetitions l=1 and the maximum number ofrepetitions l_(max) are set. Further, a reception LLR: λ_(n) is input,and B_(mn(i)) ^(C) is obtained as given by the following Equation (12),assuming an LLR of the minimum k value of the m-th row at the initialtime is β_(mn(i)) ⁽⁰⁾. As a sign of the LLR: β_(mn) ⁽⁰⁾ in the m-th rowat the initial time, sgn(λn) is input, and S_(m) is obtained as shown bythe following Equation (12):

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 9} \right\rbrack & \; \\{{{B_{{mn}^{\prime}}^{C} = {{\beta_{{mn}{(i)}}^{(0)}} = {\min\limits_{n \in {{N{(m)}}\backslash {\{{{n{(1)}},{n{(2)}},\mspace{11mu} \ldots \mspace{14mu},{n{({i - 1})}}}\}}}}\left\lbrack {\lambda_{n}} \right\rbrack}}},{\forall{i \in \left\lbrack {1,k} \right\rbrack}}}{S_{m} = {\prod\limits_{n \in {N{(m)}}}{{sgn}\left( \lambda_{n} \right)}}}{{n(i)} = {\arg {\min\limits_{n \in {{N{(m)}}\backslash {\{{{n{(1)}},{n{(2)}},\mspace{11mu} \ldots \mspace{14mu},{n{({i - 1})}}}\}}}}\left\lbrack {\lambda_{n}} \right\rbrack}}}{{n(0)} = \varphi}} & (12)\end{matrix}$

where B_(mn(i)) ^(C) is an absolute value of the LLR: β_(mn(i)) of theminimum k value of the m-th row and is used in common in the parallelprocessing, and n(i) is a column number of the minimum i-th LLR inB_(mn(i)) ^(C).

(Row Processing Step)

In the present embodiment, a starting column of each row processing isarbitrary. At the stage where the processing ends up to the finalcolumn, decoding is performed again cyclically from the first column. Asthe row processing, the repetition first-time LLR: α_(mn) ⁽¹⁾ of the bitn to be sent from the check node m to the bit node n is updated for0≦g≦G−1, g·N_(G)+1≦n≦(g+1)·N_(G), and for each m, where G is a parallelnumber, N_(G) is a column number that each parallelized decoding circuitprocesses, and G·N_(g)=N, by the following Equation (13):

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 10} \right\rbrack & \; \\\begin{matrix}{\alpha_{mn}^{(1)} = {\prod\limits_{\underset{n^{\prime} < {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}{\backslash n}}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(1)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}{\backslash n}}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}\left\lfloor B_{{mn}^{\prime}}^{C} \right\rfloor}}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}\end{matrix} & (13) \\{S_{m}^{\prime} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)}}} & \;\end{matrix}$

Specifically, for example, G row processing units allocated to the Gcolumns, into which the column is divided for each column number: N_(G),perform the row processing in parallel. The G row processing unitsexecute the parallel processing, and perform the same operation as thatof the “Cyclic approximated min algorithm”, except that all theprocessing units use the same B_(mn) ^(C).

(Column Processing Step)

Next, as the column processing, the repetition first-time LLR: β_(mn)⁽¹⁾ of the bit n to be sent from the bit node n to the check node m isupdated for 0≦g≦G−1, g·N_(G)+1≦n≦(g+1)·N_(G), and for each m by thefollowing Equation (14). That is, in the present embodiment, after therow processing is performed in parallel as described above, forrespective columns are performed in parallel the column processingrepresented by the following Equation (14):

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 11} \right\rbrack & \; \\{{{\beta_{mn}^{(1)} = {\lambda_{n} + {\sum\limits_{m^{\prime} \in {{M{(n)}}\backslash m}}\alpha_{m^{\prime}n}^{(1)}}}}{S_{m} = {S_{m}^{\prime} \cdot {{sgn}\left( \beta_{mn}^{(1)} \right)}}}{{n(i)} = {\arg {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash {\{{{n{(1)}},{n{(2)}},\mspace{11mu} \ldots \mspace{14mu},{n{({i - 1})}},{n{(i)}}}\}}}}\left\lbrack {B_{{mn}^{\prime}}^{C},{\beta_{mn}^{(1)}}} \right\rbrack}}}B_{{mn}{(i)}}^{C} = {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash {\{{{n{(1)}},{n{(2)}},\mspace{11mu} \ldots \mspace{14mu},{n{({i - 1})}},{n{(i)}}}\}}}}\left\lbrack {B_{{mn}^{\prime}}^{C},{\beta_{mn}^{(1)}}} \right\rbrack}},{\forall{i \in \left\lbrack {1,k} \right\rbrack}}} & (14)\end{matrix}$

To perform a hard decision for each n, the repetition first-timeposterior value β_(n) ⁽¹⁾ of the bit n is updated by the followingEquation (15):

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 12} \right\rbrack & \; \\{\beta_{n}^{(1)} = {\lambda_{n} + {\sum\limits_{m^{\prime} \in {M{(n)}}}\alpha_{n}^{(1)}}}} & (15)\end{matrix}$

The stop regulation is the same as that of the “Cyclic approximated minalgorithm” described above.

Described below is a configuration and operation of the LDPC decoder 5according to the second embodiment that achieves the above “Overlappedcyclic approximated min algorithm”.

FIG. 13 is a configuration example of the LDPC decoder 5 according tothe present embodiment. The LDPC decoder 5 includes the reception-LLRcalculating unit 11 that calculates the reception LLR from the receptioninformation, and a decoding core unit 12 a that performs decoding of thepresent embodiment. The decoding core unit 12 a includes anintermediate-result retaining unit 21 a including a memory which storestherein an intermediate result (intermediate value) of decoding, rowprocessing units 22-1 to 22-G that perform row processing (parallelprocessing) according to the present embodiment, column processing units23-1 to 23-G that perform column processing (parallel processing) of thepresent embodiment, the decoding-result determining unit 24 thatperforms a hard decision of a posterior value in the column processingand an error determination of a parity check result, as a stopregulation according to the present embodiment, and a controller 25 athat performs a repetition control of decoding.

In FIG. 13, the LDPC decoder 5 of the present embodiment uses in commonB_(mn) ^(C) and S_(m) retained by the intermediate-result retaining unit21 a following Equations (12), (13), and (14), when respective rowprocessing units and respective column processing units performprocessing in parallel, thereby updating B_(mn) ^(C) and S_(m),respectively. With this parallel processing, B_(mn) ^(C) and S_(m) arerapidly updated according to the parallel number, which substantiallyreduces the number of decoding iterations.

According to the present embodiment, in the parallel processing, whencalculation of the same row occurs in the same clock and when the samebuffer is referenced, various measures are taken, such as a memoryaccess priority order is set to each processing unit, a memory bank ispartitioned, and the timing of the memory access is adjusted using ashift register.

As described above, in the “Overlapped cyclic approximated minalgorithm” according to the present embodiment, the row processing andthe column processing are performed in parallel using the “Cyclicapproximated min algorithm” described above. Further, theintermediate-result retaining unit that retains the minimum k valueupdated in each column processing performed in parallel is shared, andthe minimum k value is updated in each column processing performed inparallel. With this arrangement, the number of decoding iterations canbe substantially reduced as compared with the decrease according to the“Min-Sum algorithm” and the first embodiment described above.

FIG. 14 depicts a performance comparison regarding the number ofrepetitions. Specifically, the repetition performance of the “Overlappedcyclic approximated min algorithm” is compared with the repetitionperformance of the “Cyclic approximated min algorithm”, and the “Min-Sumalgorithm”, respectively when the parallel number is 2, in the statethat the number of decoding iterations is fixed. In FIG. 14, when thenumber of decoding iterations is limited to a small number, it can beconfirmed that the decoding performance of the “Cyclic approximated minalgorithm” is higher than the decoding performance of the conventionalmethod of the “Min-Sum algorithm”, and that the “Overlapped cyclicapproximated min algorithm” has the decoding performance of the samelevel of the decoding performance by about the half number of decodingiterations of the “Cyclic approximated min algorithm”. In FIG. 14, thenumber of decoding iterations is about a half because the parallelnumber is 2. When the “Overlapped cyclic approximated min algorithm” isused, the number of repetitions becomes “1/parallel number” of the“Cyclic approximated min algorithm”.

Third Embodiment

A receiving device and a decoding method according to a third embodimentare explained below. In the present embodiment, the process of updatingonly the absolute value of the LLR of the minimum k value and thedecoding using the approximate minimum value in the “Cyclic approximatedmin algorithm” according to the first embodiment or the “Overlappedcyclic approximated min algorithm” according to the second embodimentare cyclically applied to the “Normalized BP-based algorithm” as theknown decoding algorithm using the “Min-Sum algorithm”.

Before explaining the decoding algorithm of the present embodiment, theknown “Normalized BP-based algorithm” that is the basis the decodingalgorithm is shown below. The row processing different from that of the“Min-Sum algorithm” is explained.

(Row Processing Step)

The row processing of the above “Normalized BP-based algorithm” can begeneralized by the following Equation (16). In this case, as the rowprocessing, the repetition first-time LLR: α_(mn) ⁽¹⁾ is updated foreach of m and n by the following Equation (16), where A is a constantcalled a normalization factor. In the “Normalized BP-based algorithm”,the repetition first-time LLR obtained by the “Min-Sum algorithm” iscorrected by the normalization factor A.

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 13} \right\rbrack & \; \\\begin{matrix}{\alpha_{mn}^{(1)} = {2{\tanh^{1}\left( {\prod\limits_{n^{\prime} \in {{N{(m)}}{\backslash n}}}{\tanh\left( \frac{\beta_{{mn}^{\prime}}^{({l - 1})}}{2} \right)}} \right)}}} \\{= {2{\tanh^{- 1}\left( {\prod\limits_{n^{\prime} \in {{N{(m)}}{\backslash n}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\prod\limits_{n^{\prime} \in {{N{(m)}}{\backslash n}}}{\tanh\left( \frac{\beta_{{mn}^{\prime}}^{({l - 1})}}{2} \right)}}}} \right)}}} \\{= {\prod\limits_{n^{\prime} \in {{N{(m)}}{\backslash n}}}{{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot 2}{\tanh^{- 1}\left( {\prod\limits_{n^{\prime} \in {{N{(m)}}{\backslash n}}}{\tanh \left( \frac{\beta_{{mn}^{\prime}}^{({l - 1})}}{2} \right)}} \right)}}}} \\{\approx {\frac{1}{A}{\prod\limits_{n^{\prime} \in {{N{(m)}}{\backslash n}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N{(m)}}{\backslash n}}}{\beta_{{mn}^{\prime}}^{({l - 1})}}}}}}}\end{matrix} & (16)\end{matrix}$

The decoding algorithm when the “Cyclic approximated min algorithm” orthe “Overlapped cyclic approximated min algorithm” is applied to the“Normalized BP-based algorithm” is explained below. In the following,explanations are omitted for the processing (initialization, columnprocessing, and stop regulation) similar to that of the “Cyclicapproximated min algorithm” or the “Overlapped cyclic approximated minalgorithm”. The row processing different from that of the “Cyclicapproximated min algorithm” or the “Overlapped cyclic approximated minalgorithm” is explained below.

(Row Processing Step Using Cyclic Approximated min Algorithm)

In the present embodiment, a starting column of the row processing isarbitrary. At the stage where the processing ends to the last column,decoding is performed again cyclically from the first column. The rowprocessing of the decoding algorithm according to the present embodimentusing the “Cyclic approximated min algorithm” can be generalized by thefollowing Equation (17). In this case, as the row processing, therepetition first-time LLR: α_(mn) ⁽¹⁾ is updated for each of m and n bythe following Equation (17). That is, the repetition first-time LLRobtained by the “Cyclic approximated min algorithm” is corrected by thenormalization factor A in the following Equation (17):

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 14} \right\rbrack & \; \\\begin{matrix}{\alpha_{mn}^{(1)} = {\frac{1}{A}{\prod\limits_{\underset{n^{\prime} < n}{n^{\prime} \in {{N{(m)}}{\backslash n}}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(1)} \right)} \cdot}}}} \\{{\prod\limits_{\underset{n^{\prime} > n}{n^{\prime} \in {{N{(m)}}{\backslash n}}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}} \\{= {\frac{1}{A}{S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}} \\{= {\frac{1}{A}{S_{m}^{\prime} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}{\left\lbrack B_{{mn}^{\prime}} \right\rbrack.}}}}}\end{matrix} & (17)\end{matrix}$

(Row Processing Step Using Overlapped Cyclic Approximated min Algorithm)

The row processing of the decoding algorithm according to the presentembodiment using the “Overlapped cyclic approximated min algorithm” canbe generalized by the following Equation (18). In this case, as the rowprocessing, the repetition first-time LLR: α_(mn) ⁽¹⁾ is updated for0≦g≦G−1, g·N_(G)+1≦n≦(g+1)·N_(G), and for each m by the followingEquation (18). That is, the repetition first-time LLR obtained by the“Overlapped cyclic approximated min algorithm” is corrected by thenormalization factor A in the following Equation (18):

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 15} \right\rbrack & \; \\\begin{matrix}{\alpha_{mn}^{(1)} = {\frac{1}{A}{\prod\limits_{\underset{n^{\prime} < {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}{\backslash n}}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}{\backslash n}}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot}}}}}} \\{{\min\limits_{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}} \\{= {\frac{1}{A}{S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}} \\{= {\frac{1}{A}{S_{m}^{\prime} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}}\end{matrix} & (18)\end{matrix}$

In the decoding algorithm according to the present embodiment, after therow processing step is performed as described above, processing based onthe column processing and the stop regulation similar to those of the“Cyclic approximated min algorithm” or the “Overlapped cyclicapproximated min algorithm” is performed to obtain the final coderesult.

Characteristic operations of the row processing unit of the LDPC decoder5 that executes the decoding algorithm of the present embodiment areexplained below with reference to the drawings. The entire configurationof the LDPC decoder 5 is similar to that shown in FIG. 5 or FIG. 13.

FIG. 15 is a configuration example of row processing units 22, 22-1 to22-G that perform row processing of the present embodiment. The rowprocessing unit includes a minimum-value selecting unit 31 a.Configurations similar to those explained with reference to FIG. 6 aredenoted by like reference numerals, and explanations thereof are notrepeated. The minimum value selecting unit 31 a according to the presentembodiment corrects the minimum value (Min 1LLR or Min 2LLR) of the LLRread from the intermediate-result retaining unit 21 (or 21 a), using thenormalization factor A, for example. Specifically, the minimum valueselecting unit 31 a performs the normalization by dividing the LLRminimum value by A.

As described above, according to the present embodiment, the “Cyclicapproximated min algorithm” or the “Overlapped cyclic approximated minalgorithm” is applied to the “Normalized BP-based algorithm” having thebetter performance than that of the “Min-Sum algorithm”. With thisarrangement, effects similar to those of the first and secondembodiments can be obtained. Further, performance close to that of the“Sum-Product algorithm” can be achieved, regardless of the circuitamount substantially equivalent to that of the “Min-Sum algorithm”.

In the present embodiment, the “Cyclic approximated min algorithm” orthe “Overlapped cyclic approximated min algorithm” is applied to the“Normalized BP-based algorithm”. Alternatively, the “Cyclic approximatedmin algorithm” or the “Overlapped cyclic approximated min algorithm” canalso be applied to the known “Offset BP-based algorithm” or otheralgorithm. In this case also, effects similar to those described abovecan be obtained.

Fourth Embodiment

A receiving device and a decoding method according to a fourthembodiment are explained below. In the present embodiment, the processof updating only the absolute value of the LLR of the minimum k valueand the decoding using the approximate minimum value in the “Cyclicapproximated min algorithm” according to the first embodiment or the“Overlapped cyclic approximated min algorithm” according to the secondembodiment are cyclically applied to the “δ min algorithm” as the knowndecoding algorithm having superior correction performance of LLR: β_(mn)to that of the “Normalized BP-based algorithm” or the “Offset BP-basedalgorithm”.

Before explaining the decoding algorithm of the present embodiment, theknown “δ min algorithm” that is the basis of the decoding algorithm isexplained. The row processing different from that of the “Min-Sumalgorithm” is explained below.

(Row Processing Step)

The row processing of the above “δ min algorithm” can be generalized bythe following Equation (19). In this case, as the row processing, therepetition first-time LLR: α_(mn) ⁽¹⁾ is updated for each of m and n bythe following Equation (19). In the row processing of the “δ minalgorithm”, α_(mn) ⁽¹⁾ is calculated by calculating Θ from the absolutevalue: |β_(mn′) ^((i−1))| of the LLR updated at the repetition l−1-thtime.

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 16} \right\rbrack & \; \\{{\alpha_{m,n}^{(i)} = {\prod\limits_{n^{\prime} \in {{N{(m)}}{\backslash n}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({i - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N{(m)}}{\backslash n}}}{\Theta}\left\lbrack {\beta_{m,n^{\prime}}^{({i - 1})}} \right\rbrack}}}}{{\underset{n \in A}{\Theta}\left( I_{n} \right)} \equiv {I_{1}{\Theta I}_{2}\Theta \mspace{14mu} \ldots \mspace{14mu} {\Theta I}_{A}}}{{a\; \Theta \; b} \equiv {\max \left( {{{\min \left( {a,b} \right)} - \Delta},0} \right)}}\Delta \equiv {\max \left( {{0.9 - {{{a - b}}/2}},0} \right)}} & (19)\end{matrix}$

The decoding algorithm when the “Cyclic approximated min algorithm” orthe “Overlapped cyclic approximated min algorithm” is applied to the “δmin algorithm” is explained below. In the following, explanations areomitted for the processing (initialization, column processing, and stopregulation) similar to that of the “Cyclic approximated min algorithm”or the “Overlapped cyclic approximated min algorithm”. The rowprocessing different from that of the “Cyclic approximated minalgorithm” or the “Overlapped cyclic approximated min algorithm” isexplained below. In the present embodiment, a starting column of the rowprocessing is arbitrary. At the stage where the processing ends to thelast column, decoding is performed again cyclically from the firstcolumn.

(Row Processing Step Using Cyclic Approximated min Algorithm)

For example, the row processing of the decoding algorithm according tothe present embodiment using the “Cyclic approximated min algorithm” canbe generalized by the following Equation (20). In this case, as the rowprocessing, the repetition first-time LLR: α_(mn) ⁽¹⁾ is updated for1≦n≦N and for each m by the following Equation (20). In the rowprocessing of the decoding algorithm, α_(mn) ⁽¹⁾ is calculated bycalculating Θ from the absolute value: B_(mn′) of the LLR of the minimumk value updated at the repetition l−1-th time.

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 17} \right\rbrack & \; \\\begin{matrix}{\alpha_{mn}^{(1)} = {\prod\limits_{\underset{n^{\prime} < n}{n^{\prime} \in {{N{(m)}}{\backslash n}}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(1)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > n}{n^{\prime} \in {{N{(m)}}{\backslash n}}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}\end{matrix} & (20)\end{matrix}$

(Row Processing Step Using Overlapped Cyclic Approximated min Algorithm)

The row processing of the decoding algorithm according to the presentembodiment using the “Overlapped cyclic approximated min algorithm” canbe generalized by the following Equation (21). In this case, as the rowprocessing, the repetition first-time LLR: α_(mn) ⁽¹⁾ is updated for0≦g≦G−1, g·N_(G)+1≦n≦(g+1)·N_(G), and for each m by the followingEquation (21). In the row processing of this decoding algorithm, α_(mn)⁽¹⁾ is calculated by calculating Θ from the absolute value: β_(mn′) ^(C)of the LLR of the minimum k value updated by the parallel processing atthe repetition l−1-th time.

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 18} \right\rbrack & \; \\\begin{matrix}{\alpha_{mn}^{(1)} = {\prod\limits_{\underset{n^{\prime} < {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}{\backslash n}}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(1)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}{\backslash n}}}}{{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot \underset{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}{\Theta}}\left\lfloor B_{{mn}^{\prime}}^{C} \right\rfloor}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}{\Theta}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {{\underset{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}{\Theta}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}.}}}\end{matrix} & (21)\end{matrix}$

In the decoding algorithm according to the present embodiment, after therow processing step is performed as described above, processing based onthe column processing and the stop regulation similar to those of the“Cyclic approximated min algorithm” or the “Overlapped cyclicapproximated min algorithm” is performed to obtain the final coderesult.

Characteristic operations of the row processing unit of the LDPC decoder5 that executes the decoding algorithm of the present embodiment areexplained below with reference to the drawings. The entire configurationof the LDPC decoder 5 is similar to that shown in FIG. 5 or FIG. 13.

FIG. 16 is a configuration example of the row processing units 22, 22-1to 22-G that perform row processing of the present embodiment.Constituent elements similar to those described with reference to FIG. 6are denoted by like reference numerals, and explanations thereof are notrepeated. While the LDPC decoder 5 shown in FIG. 5 is explained as oneexample, the present embodiment can also be similarly applied to theLDPC decoder 5 shown in FIG. 13.

A minimum-value selecting unit 31 b according to the present embodimentreads the Min 1LLR(B_(mn(1))), Min 2LLR(B_(mn(2))), Min kLLR(B_(mn(k))),and their column numbers from the intermediate-result retaining unit 21,and the calculating unit performs the Θ calculation. That is, in theminimum-value selecting unit 31 b according to the present embodiment,the calculating unit performs the following calculation in the “δ minalgorithm”, to B_(mn(k)) in which the n-th column to be processed doesnot coincide with the column number n(k) of B_(mn(k)) retained in theintermediate-result retaining unit 21.

For example, the calculating unit obtains the updated value |α_(mn)⁽¹⁾|(=Θ[(B_(mn′)]) excluding the sign as represented by the followingEquation (22):

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 19} \right\rbrack & \; \\{\underset{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack} & (22)\end{matrix}$

Further, by limiting the LLR to be calculated from the k value to theminimum 3 values, calculations can be reduced. The calculating unitobtains the updated value |α_(mn) ⁽¹⁾|(=Θ[(B_(mn′)]) excluding the signas represented by the following Equation (23):

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 20} \right\rbrack & \; \\{{{{if}\mspace{14mu} \left( {n = n_{(1)}} \right){\underset{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {B_{{mn}_{(2)}}\Theta \; B_{{mn}_{(3)}}}}{{{else}\mspace{14mu} {if}\mspace{14mu} \left( {n = n_{(2)}} \right){\underset{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {B_{{mn}_{(1)}}\Theta \; B_{{mn}_{(3)}}}}{{{else}{\underset{n^{\prime} \in {{N_{k}{(m)}}{\backslash n}}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {B_{{mn}_{(1)}}{\Theta B}_{{mn}_{(2)}}}}} & (23)\end{matrix}$

While the LLR to be calculated is limited from the k value to theminimum 3 values in the above example, the embodiment can also beapplied to the case that the LLR is limited to the minimum 4, 5, . . .values.

As described above, according to the present embodiment, the “Cyclicapproximated min algorithm” or the “Overlapped cyclic approximated minalgorithm” is applied to the “δ min algorithm” having the betterperformance than that of the “Min-Sum algorithm”. With this arrangement,effects similar to those of the first and second embodiments can beobtained. Further, performance close to that of the “Sum-Productalgorithm” can be achieved, regardless of the circuit amountsubstantially equivalent to that of the “Min-Sum algorithm”. In thepresent embodiment, description is made for the case that the minimumvalue of the absolute values of the LLR for the row processing iscorrected to the optimum value based on a predetermined correctionequation prescribed by the known “δ min algorithm”. However, thecorrection equation is not limited to this, and the correction equationprescribed by the algorithm other than the “δ min algorithm” can also beused. In this case also, effects similar to those described above can beobtained.

FIG. 17 depicts a result of comparison between a decoding algorithmhaving the “Cyclic approximated min algorithm” or the “Overlapped cyclicapproximated min algorithm” applied to the “δ min algorithm” and the“Sum-Product algorithm”. For example, overlap5delta10 is a decodingalgorithm (parallel number: 2, minimum 5 values, l=10) according to thepresent embodiment using the “Overlapped cyclic approximated minalgorithm”, and Cyclic5delta50 is a decoding algorithm (withoutparallel, minimum 5 values, l=50) according to the present embodimentusing the “Cyclic approximated min algorithm”. Sum-Product100 is the“Sum-Product algorithm” (l=100). These are substantially overlapped.From this result, by applying the “Cyclic approximated min algorithm” orthe “Overlapped cyclic approximated min algorithm” to the “δ minalgorithm”, performance approximately the same as that of the“Sum-Product algorithm” can be obtained. Further, the number of decodingiterations can also be substantially reduced.

Fifth Embodiment

A receiving device and a decoding method according to a fifth embodimentare explained below. In the present embodiment, the process of updatingonly the absolute value of the LLR of the minimum k value and thedecoding using the approximate minimum value in the “Cyclic approximatedmin algorithm” according to the first embodiment or the “Overlappedcyclic approximated min algorithm” according to the second embodimentare cyclically applied to the “Sum-Product algorithm”.

Before explaining the decoding algorithm of the present embodiment, theknown “Sum-Product algorithm” that is the basis of the decodingalgorithm is explained. In the present embodiment, a method ofcalculation by tabling the mathematical function, i.e., a general“Sum-Product algorithm” using a TLU (table lookup), is described. Therow processing different from that of the “Sum-Product algorithm”explained in the conventional technology is described.

(Row Processing Step (1))

The row processing of the “Sum-Product algorithm” using the TLU can begeneralized by the following Equation (24). In this case, as the rowprocessing, the repetition first-time LLR: α_(mn) ⁽¹⁾ is updated foreach of m and n by the following Equation (24). In the row processing ofthe “Sum-Product algorithm” using the TLU, a calculation using the TLUis performed to the absolute value: |β_(mn′) ^((l−1)) of the LLR updatedat the repetition l−1-th time.

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 21} \right\rbrack & \; \\{{{{\alpha_{m,n}^{(i)} = {\prod\limits_{n^{\prime} \in {{N{(m)}}{\backslash n}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({i - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N{(m)}}{\backslash n}}}{T\; L\; U}\left\lbrack {\beta_{m,n^{\prime}}^{({i - 1})}} \right\rbrack}}}}\underset{n \in A}{T\; L\; U}\left( I_{n} \right)} \equiv {T\; L\; {U\left( {I_{1},{T\; L\; {U\left( {I_{2},{\ldots \mspace{14mu} T\; L\; {U\left( {I_{{A} - 1},I_{A}} \right)}}} \right)}}} \right)}}}{{T\; L\; {U\left( {a,b} \right)}} \equiv {2{\tanh^{- 1}\left( {\tanh {\frac{a}{2} \cdot \tanh}\frac{b}{2}} \right)}}}} & (24)\end{matrix}$

(Row Processing Step (2))

The row processing of the “Sum-Product algorithm” using the TLU can alsobe achieved by the method different from the above method. For example,the row processing of the “Sum-Product algorithm” using the TLUdifferent from the above method can be generalized by the followingEquation (25). In this case, as the row processing, the repetitionfirst-time LLR: α_(mn) ⁽¹⁾ is updated for each of m and n by thefollowing Equation (25):

$\begin{matrix}\left\lbrack {{Expression}\mspace{14mu} 22} \right\rbrack & \; \\{{\alpha_{m,n}^{(i)} = {\prod\limits_{n^{\prime} \in {{N{(m)}}{\backslash n}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({i - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N{(m)}}{\backslash n}}}{\Xi}\left\lbrack {\beta_{m,n^{\prime}}^{({i - 1})}} \right\rbrack}}}}{{\underset{n \in A}{\Xi}\left( I_{n} \right)} \equiv {I_{1}\Xi \; I_{2}\Theta \mspace{14mu} \ldots \mspace{14mu} \Xi \; I_{A}}}{{a\; \Xi \; b} \equiv {{\min \left( {a,b} \right)} + {T\; L\; U\; 1\left( {{a + b}} \right)} - {T\; L\; U\; 1\left( {{a - b}} \right)}}}} & (25)\end{matrix}$

For the TLU1(x), a table is prepared in advance based on the followingEquation (26):

TLU1(x)=in(1+exp(−x))  (26)

In the “Sum-Product algorithm” using the TLU, the row processingrepresented by Equation (24) has a characteristic that while the tablebecomes large, the number of calculations is small. On the other hand,the row processing represented by Equation (25) has a characteristicthat the number of calculations is large although the table becomessmall.

The decoding algorithm when the “Cyclic approximated min algorithm” isapplied to the “Sum-Product algorithm” using the TLU is explained below.In the following, explanations are omitted for the processing(initialization, column processing, and stop regulation) similar to thatof the “Cyclic approximated min algorithm”. The row processing differentfrom that of the “Cyclic approximated min algorithm” is explained below.In the present embodiment, a starting column of the row processing isarbitrary, and at the stage where the processing ends up to the finalcolumn, decoding is performed again cyclically from the first column.

(Row Processing Step Using Cyclic Approximated min Algorithm (1))

The row processing of the decoding algorithm according to the presentembodiment having the “Cyclic approximated min algorithm” applied to theabove row processing step (1) can be generalized by the followingEquation (27). In this case, as the row processing, the repetitionfirst-time LLR: α_(mn) ⁽¹⁾ is updated for 1≦n≦N and for each m by thefollowing Equation (27). In the row processing of the decodingalgorithm, a calculation using the TLU is performed to the absolutevalue: B_(mn′) of the LLR of the minimum k value updated at therepetition l−1-th time.

$\begin{matrix}\text{[Expression~~23]} & \; \\\begin{matrix}{\alpha_{mn}^{(1)} = {\prod\limits_{\underset{n^{\prime} < n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(1)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}\end{matrix} & (27)\end{matrix}$

(Row Processing Step Using Cyclic Approximated min Algorithm (2))

The row processing of the decoding algorithm according to the presentembodiment having the “Cyclic approximated min algorithm” applied to theabove row processing step (2) can be generalized by the followingEquation (28). In this case, as the row processing, the repetitionfirst-time LLR: α_(mn) ⁽¹⁾ is updated for 1≦n≦N and for each m by thefollowing Equation (28):

$\begin{matrix}\text{[Expression~~24]} & \; \\\begin{matrix}{\alpha_{mn}^{(1)} = {\prod\limits_{\underset{n^{\prime} < n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(1)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}\end{matrix} & (28)\end{matrix}$

The decoding algorithm when the “Overlapped cyclic approximated minalgorithm” is applied to the “Sum-Product algorithm” using the TLU isexplained below. In the following, explanations are omitted for theprocessing (initialization, column processing, and stop regulation)similar to that of the “Overlapped cyclic approximated min algorithm”.The row processing different from that of the “Overlapped cyclicapproximated min algorithm” is explained below.

(Row Processing Step Using Overlapped Cyclic Approximated min Algorithm(1))

The row processing of the decoding algorithm according to the presentembodiment having the “Overlapped cyclic approximated min algorithm”applied to the above row processing step (1) can be generalized by thefollowing Equation (29). In this case, as the row processing, therepetition first-time LLR: α_(mn) ⁽¹⁾ is updated for 0≦g≦G−1,g·N_(G)+1≦n≦(g+1)·N_(G), and for each m by the following Equation (29).In the row processing of this decoding algorithm, a calculation usingthe TLU is performed to the absolute value: B_(mn′) ^(C) of the LLR ofthe minimum k value updated by the parallel processing at the repetitionl−1-th time.

$\begin{matrix}\text{[Expression~~25]} & \; \\\begin{matrix}{\alpha_{mn}^{(1)} = {\prod\limits_{\underset{n^{\prime} < {g \cdot N_{G}}}{n^{\prime} \in {N{(m)}}}\backslash \; n}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(1)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > {g \cdot N_{G}}}{n^{\prime} \in {N{(m)}}}\backslash \; n}{{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot \underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}}\left\lfloor B_{{mn}^{\prime}}^{C} \right\rfloor}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}\end{matrix} & (29)\end{matrix}$

(Row Processing Step Using Overlapped Cyclic Approximated min Algorithm(2))

The row processing of the decoding algorithm according to the presentembodiment having the “Overlapped cyclic approximated min algorithm”applied to the above row processing step (2) can be generalized by thefollowing Equation (30). In this case, as the row processing, therepetition first-time LLR: α_(mn) ⁽¹⁾ is updated for 0≦g≦G−1,g·N_(G)+1≦n≦(g+1)·N_(G), and for each m by the following Equation (30):

$\begin{matrix}\text{[Expression~~26]} & \; \\\begin{matrix}{\alpha_{mn}^{(1)} = {\prod\limits_{\underset{n^{\prime} < {g \cdot N_{G}}}{n^{\prime} \in {N{(m)}}}\backslash \; n}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(1)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > {g \cdot N_{G}}}{n^{\prime} \in {N{(m)}}}\backslash \; n}{{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot \underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}}\left\lfloor B_{{mn}^{\prime}}^{C} \right\rfloor}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}\end{matrix} & (30)\end{matrix}$

Characteristic operations of the row processing unit of the LDPC decoder5 that executes the decoding algorithm of the present embodiment areexplained below with reference to the drawings. The entire configurationof the LDPC decoder 5 is similar to that shown in FIG. 5 or FIG. 13.

FIG. 18 is a configuration example of the row processing units 22, 22-1to 22-G that perform row processing of the present embodiment.Constituent elements similar to those described with reference to FIG. 6are denoted by like reference numerals, and explanations thereof are notrepeated. While the LDPC decoder 5 shown in FIG. 5 is explained as oneexample, the present embodiment can also be similarly applied to theLDPC decoder 5 shown in FIG. 13.

A minimum-value selecting unit 31 c according to the present embodimentreads the Min 1LLR(B_(mn(1))), Min 2LLR(B_(mn(2))), Min kLLR(B_(mn(k))),and their column numbers from the intermediate-result retaining unit 21,and the calculating unit performs calculation using the TLU. That is, inthe minimum-value selecting unit 31 c according to the presentembodiment, the calculating unit performs the following calculation inthe “Sum-Product min algorithm”, to B_(mn(k)) in which the n-th columnto be processed does not coincide with the column number n(k) ofB_(mn(k)) retained in the intermediate-result retaining unit 21.

For example, the calculating unit obtains the updated value excludingthe sign as represented by the following Equation (31):

$\begin{matrix}\text{[Expression~~27]} & \; \\{{\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}\mspace{14mu} {OR}\mspace{14mu} {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} & (31)\end{matrix}$

Further, by limiting the LLR to be calculated from the k value to theminimum 3 values, calculations can be reduced. The calculating unitobtains the updated value excluding the sign as represented by thefollowing Equation (32):

$\begin{matrix}\text{[Expression~~28]} & \; \\{{{{if}\mspace{14mu} \left( {n = n_{(1)}} \right){\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {{{TLU}\left( {B_{{mn}_{(2)}},B_{{mn}_{(3)}}} \right)}\mspace{14mu} {OR}}}{{\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack} = {B_{{mn}_{(2)}}\Xi \; B_{{mn}_{(3)}}}}{{{else}\mspace{14mu} {{if}\text{}\left( {n = n_{(2)}} \right)}{\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {{{TLU}\left( {B_{{mn}_{(1)}},B_{{mn}_{(3)}}} \right)}\mspace{14mu} {OR}}}{{\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack} = {B_{{mn}_{(1)}}\Xi \; B_{{mn}_{(3)}}}}{{{else}\mspace{14mu} {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {{{TLU}\left( {B_{{mn}_{(1)}},B_{{mn}_{(2)}}} \right)}\mspace{14mu} {OR}}}{{\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack} = {B_{{mn}_{(1)}}\Xi \; B_{{mn}_{(2)}}}}} & (32)\end{matrix}$

While the LLR to be calculated is limited from the k value to theminimum 3 values in the above explanation as an example, the embodimentcan also be applied to the case that the LLR is limited to the minimum4, 5, . . . values.

As described above, according to the present embodiment, the “Cyclicapproximated min algorithm” or the “Overlapped cyclic approximated minalgorithm” is applied to the “Sum-Product algorithm” using the TLU. Withthis arrangement, although calculations and the required memory capacityincrease as compared with other embodiments, decoding performance can beimproved. While the “Sum-Product algorithm” using the TLU is explainedin the present embodiment, the principle can be similarly applied toother decoding algorithm for performing the TLU to the mathematicalfunction. In the present embodiment, the TLU prescribed by the known“Sum-Product algorithm” is used for the minimum value of the absolutevalues of the LLR for the row processing. However, the TLU is notlimited to the above, and the TLU other than the TLU prescribed by the“Sum-Product algorithm” can also be used. In this case also, effectssimilar to the above effects can be obtained.

Sixth Embodiment

A communication apparatus and a decoding method according to a sixthembodiment are explained below. According to the present embodiment, thenumber of repetitions can be further reduced by relating the decoding toa serial decoding in a complete bit unit.

As in the above embodiment, FIG. 5-1 depicts a configuration of the LDPCdecoder 5 according to the present embodiment. The LDPC decoder 5includes the reception-LLR calculating unit 11 that calculates thereception LLR from the reception information, and the decoding core unit12 that performs decoding according to the present embodiment. Thedecoding core unit 12 includes the intermediate-result retaining unit 21configured by a memory which stores therein an intermediate result(intermediate value) of decoding, the row processing unit 22 thatperforms row processing according to the present embodiment, the columnprocessing unit 23 that performs column processing according to thepresent embodiment, the decoding-result determining unit 24 thatperforms a hard decision of a posterior value in the column processingand an error determination of a parity check result, as a stopregulation according to the present embodiment, and the controller 25that performs a repetition control of decoding.

The decoding algorithm according to the present embodiment is a methodof cyclically updating only the absolute value of the LLR of the minimumk value. Because this algorithm is the method of decoding using anapproximate minimum value instead of an accurately minimum value and isthe serial decoding method, this algorithm is hereinafter called the“Serial cyclic approximated min algorithm”. The minimum k valuerepresents “from the minimum value to the k-th value in the ascendingorder.

The “Serial cyclic approximated min algorithm” executed in the receivingdevice is shown below.

(Initialization Step)

First, the number of repetitions l=1 and the maximum number ofrepetitions l_(max) are set. The LLR of the minimum k value of the m-throw at the initial time is set as β_(mn(i)) ⁽⁰⁾, and a reception LLR:λ_(n) is input, thereby obtaining B_(mn(i)) as represented by thefollowing Equation (33). As a sign of the LLR: β_(mn) ⁽⁰⁾ of the m-throw at the initial time, sgn(λ_(n)) is input, thereby obtaining S_(m) asrepresented by the following Equation (33):

$\begin{matrix}\text{[Expressing~~29]} & \; \\{{{B_{{mn}{(i)}} = {{\beta_{{mn}{(i)}}^{(0)}} = {\min\limits_{n \in {{N{(m)}}\backslash \; {\{{{n{(1)}},{n{(2)}},\; \ldots \;,{n{({i - 1})}}}\}}}}\left\lbrack {\lambda_{n}} \right\rbrack}}},{\forall{i \in \left\lbrack {1,k} \right\rbrack}}}{S_{m} = {\prod\limits_{n \in {N{(m)}}}{{sgn}\left( \lambda_{n} \right)}}}{{n(i)} = {\arg \; {\min\limits_{n \in {{N{(m)}}\backslash \; {\{{{n{(1)}},{n{(2)}},\; \ldots \;,{n{({i - 1})}}}\}}}}\left\lbrack {\lambda_{n}} \right\rbrack}}}{{n(0)} = \varphi}} & (33)\end{matrix}$

where B_(mn(i)) is an absolute value of the LLR: B_(mn(i)) of theminimum k value of the m-th row, n(i) is a column number of the minimumi-th LLR in B_(mn(i)), and S_(m) is a product of signs (+ or −) of theLLR: β_(mn) of the m-th row.

(Row Processing Step 1)

In the present embodiment, a starting column of the row processing isarbitrary. At the stage where the processing ends to the last column,decoding is performed again cyclically from the first column. As the rowprocessing, the repetition first-time LLR: α_(mn) ⁽¹⁾ of the bit n to besent from the check node m to the bit node n is updated for 1≦n≦N andfor each m by the following Equation (34):

$\begin{matrix}\text{[Expression~~30]} & \; \\{\begin{matrix}{\alpha_{mn}^{(l)} = {\prod\limits_{\underset{n^{\prime} < n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(l)} \right)} \cdot}}} \\{{\prod\limits_{\underset{n^{\prime} > n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}\end{matrix}{S_{m}^{\prime} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)}}}{\beta_{n}^{(l)} = {\lambda_{n} + {\sum\limits_{m \in {M{(n)}}}\alpha_{mn}^{(l)}}}}} & (34)\end{matrix}$

Specifically, when the current column number is n, a column number thatsatisfies “n′<n” takes the product of signs of the LLR: β_(mn′) ⁽¹⁾updated in the first-time column processing, and a column number thatsatisfies “n′>n” takes the product of signs of the LLR: β_(mn′) ^((l−1))updated in the (l−1)-th time column processing. A result of multiplyingthese results by the minimum LLR: min [β_(mn′)] in the minimum k valueof the m-th row is set as the updated LLR: β_(mn) ⁽¹⁾ of the columnnumber n. In the present embodiment, the term of multiplying the productof the signs of β_(mn′) ⁽¹⁾ by the product of the signs of β_(mn′)^((l−1)) is substituted by the term of multiplying S_(m) updated at the(l−1)-th time by the sign of β_(mn′) updated at the (l−1)-th time. Withthis arrangement, calculations and the required memory capacity can bereduced. N_(k)(m) in Equation (34) is the set of n(i) of the m-th row,and is expressed as N_(k)(m)={n(1), n(2), . . . , n(k)}

(Column Processing Step)

Next, as the column processing, the repetition first-time LLR: β_(mn)⁽¹⁾ of the bit n to be sent from the bit node n to the check node m isupdated by the following Equation (35) for each m of the column number nperformed at the row processing step 1. At the subsequent columnprocessing step and the row processing step 2, calculation is performedin order for each row starting from the one with the smallest rownumber, for example. However, when all rows having “1” standing areexecuted without overlapping, the calculation can be performed in anyorder.

$\begin{matrix}\text{[Expression~~31]} & \; \\{{\beta_{mn}^{(l)} = {{\lambda_{n} + {\sum\limits_{m^{\prime} \in {{M{(n)}}\backslash \; m}}\alpha_{m^{\prime}n}^{\prime {(l)}}}} = {\beta_{n}^{(l)} - \alpha_{mn}^{(l)}}}}{S_{m} = {S_{m}^{\prime} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)}}}{{n_{i} = {\arg {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash {\{{n_{1},n_{2},\; \ldots \;,n_{i - 1},n_{i},n}\}}}}\left\lbrack {B_{{mn}^{\prime}},{\beta_{mn}^{(l)}}} \right\rbrack}}},{B_{{mn}_{i}} = {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; {\{{n_{1},n_{2},\; \ldots \;,n_{i - 1},n_{i},n}\}}}}\left\lbrack {B_{{mn}^{\prime}},{\beta_{mn}^{(l)}}} \right\rbrack}},{\forall{i \in \left\lbrack {1,k} \right\rbrack}}}} & (35)\end{matrix}$

Specifically, in the column number n, a result of the addition of thereception LLR: λ_(n) and a total value of the LLR: α_(m′n) ⁽¹⁾ otherthan the m-th row LLR updated in the first-time row processing isexpressed as the updated LLR: β_(mn′) ⁽¹⁾. This calculation can also beobtained by subtracting α_(m′n) ⁽¹⁾ from β_(n) ⁽¹⁾. The above S_(m)′ ismultiplied by the sign (+ or −) of β_(mn) ⁽¹⁾ updated in the first-timecolumn processing, thereby updating S_(m) to be used in the rowprocessing. The two equations in Equation (35) prescribe the sortprocess (minimum k value) of B_(mn(1)).

(Row Processing Step 2)

Next, as the row processing again, the repetition first-time LLR:α′_(mn) ⁽¹⁾ of the bit n to be sent from the check node m to the bitnode n is updated, for the same m executed in the column processing ofthe column number n, by the following Equation (36):

$\begin{matrix}\text{[Expression~~32]} & \; \\{{\alpha_{mn}^{\prime {(l)}} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}{S_{m}^{\prime} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)}}}{\beta_{n}^{(l)} = {\beta_{mn}^{(l)} + \alpha_{mn}^{\prime {(l)}}}}} & (36)\end{matrix}$

Specifically, as the row processing again, α′_(mn) ⁽¹⁾ is updated. Theupdated α′_(mn) ⁽¹⁾ is added to β_(mn) ⁽¹⁾ using the updated result,thereby updating β_(n) ⁽¹⁾. Thereafter, by returning to the columnprocessing step, calculation is repeated until when the calculation iscompleted for all m of the column number n. When the processes at thecolumn processing step and the row processing step end for all rows mhaving “1” standing in the check matrix of the column number n, theprocess control moves to the stop regulation.

(Stop Regulation)

Thereafter, when the repetition first-time posterior value β_(n) ⁽¹⁾ ofthe bit n is “β_(n) ⁽¹⁾>0”, for example, a decoding result is “x_(n)′=1”(where x′ corresponds to the original transmission signal x). On theother hand, when “β_(n) ⁽¹⁾≦0” a decoding result is “x_(n)′=0”, and adecoding result x′=(x₁′, x₂′, . . . , X_(N)′) is obtained.

When the result of parity check is “Hx′=0” or when the number ofrepetitions is “l=1_(max)” (when any one of these condition issatisfied), a decoding result x′ in this case is output. When none ofthe two conditions is satisfied, “l=l+1” is set, and the process controlreturns to the above row processing step 1. Thereafter, the calculationis sequentially performed.

A characteristic operation of the LDPC decoder 5 that executes the above“Serial cyclic approximated min algorithm” is explained in detail withreference to a configuration diagram.

As in the above embodiment, FIG. 6 is a configuration example of the rowprocessing unit 22 that performs row processing according to the “Serialcyclic approximated min algorithm”. The row processing unit 22 includesthe minimum-value selecting unit 31, the sign calculating unit 32, andthe LLR calculating unit 33. In FIG. 6, a Min 1LLR (minimum LLR of them-th row) is B_(mn(1)), a Min 2LLR (second minimum LLR of the m-th row)is B_(mn(2)), and these are the values retained in theintermediate-result retaining unit 21. In FIG. 6, S_(m) and the “sign ofthe LLR: β_(mn) of the m-th row and n-th column of the (l−1)-th time”are also the values retained in the intermediate-result retaining unit21.

The minimum-value selecting unit 31 selects the Min 2LLR(B_(mn(2))) whenthe column number n to be row-processed coincides with the column numbern(1) of the Min 1LLR(B_(mn(1))), and selects the Min 1LLR(B_(mn(1))) inother cases, and outputs the selected result. The sign calculating unit32 multiplies the “S_(m) updated by the (l−1)-th time column processing”by the “sign of the LLR: β_(mn) of the m-th row and n-th column of the(l−1)-th time”, and outputs S_(m)′ as a result of the multiplication. Inthis case, S_(m)′ is retained in the intermediate-result retaining unit21. The LLR calculating unit 33 multiplies the minimum LLR obtained fromthe minimum-value selecting unit 31 by the multiplication result S_(m)′of the sign (+ or −) obtained from the sign calculating unit 32, therebycalculating LLR: α_(mn) ⁽¹⁾. Based on this, according to the “Min-Sumalgorithm”, the memory that has been necessary by the row weight portioncan be reduced to the k value portion.

FIG. 19 is a configuration example of the column processing unit 23 thatperforms column processing according to the “Serial cyclic approximatedmin algorithm” This column processing unit 23 includes the a adding unit41, the λ adding unit 42, the minimum-k-value comparing unit 43, and thesign calculating unit 44. In the present embodiment, k=3 is described asan example. In FIG. 19, LLR of a column weight portion, α′_(mn), α_(mn),λ_(n), S_(m)′, Min 1LLR, Min 2LLR, Min 3LLR (third-minimum LLR of them-th row) are the values retained in the intermediate-result retainingunit 21.

In the column processing unit 23, the α adding unit 41 adds all LLR:α_(mn) ⁽¹⁾ including the m-th row LLR updated in the first-time rowprocessing. Further, the λ adding unit 42 adds the reception LLR: λ_(n)to the result of the addition by the α adding unit 41, controls a switch45 to be first connected to a block below, and outputs β_(mn) ⁽¹⁾ bysubtracting α_(mn) ⁽¹⁾ from the added result. The minimum-k-valuecomparing unit 43 (k=3) receives |β_(mn) ⁽¹⁾|.

Although not shown in FIG. 19, as in the embodiment described above,when n of the n-th column to be column processed coincides with any oneof n(1), n(2), n(3) indicating the column numbers corresponding toB_(mn(1)), B_(mn(2)), B_(mn(3)), stored in the Min 1LLR, Min 2LLR, Min3LLR respectively, for example, B_(mn(1)) of n=n(i) is thinned, and theoperation as shown in FIG. 8 is performed. Specifically, informationheld in the Min 2LLR is deleted, and information held in the Min 3LLR isshifted to the Min 2LLR. A maximum value “FFFF”, for example (in thecase of 16 bits), is stored in the Min 3LLR. Accordingly, a comparisonprocess excluding the column to be processed can be performed, and atleast the Min 3LLR can be necessarily updated in the column processing.

After this processing, as shown in FIG. 19, |β_(mn) ⁽¹⁾| is comparedwith each of the Min 1LLR, Min 2LLR, Min 3LLR. When “|β_(mn) ⁽¹⁾|<Min3LLR”, the LLR of the minimum 3 value is updated. On the other hand, thesign of β_(mn) ⁽¹⁾ output by the λ adding unit 42 is retained in theintermediate-result retaining unit 21, as the “sign of the LLR: β_(mn)⁽¹⁾ of the m-th row and n-th column of the first time”. Further, thesign calculating unit 44 multiplies S_(m)′ updated in the first-time rowprocessing, by the sign of the above β_(mn) ⁽¹⁾, and updates S_(m)retained in the intermediate-result retaining unit 21, using a result ofthis multiplication. In comparing |β_(mn) ⁽¹⁾| with each of the Min1LLR, Min 2LLR, Min 3LLR, |β_(mn) ⁽¹⁾| is first compared with the Min2LLR as the center value of B_(mn(i)), and thereafter, comparison isperformed in a tree shape as shown in FIG. 19. For example, there is aneffect that the execution time becomes {(k+1)/2}/2 (where k is an oddnumber), as compared with the effect when |β_(mn) ⁽¹⁾| is compared firstwith the Min 1LLR that becomes the minimum value. When k is an evennumber, there are two center values of B_(mn(i)). In this case, any oneof the two values can be compared first. When k is an even number, thereis an effect that the execution time becomes {k/2+1}/k (where k is aneven number), as compared with the effect when |β_(mn) ⁽¹⁾| is comparedfirst with the Min 1LLR that becomes the minimum value. From the Min1LLR and Min 2LLR of this comparison result, the circuit shown in FIG. 6obtains α′_(mn) ⁽¹⁾, and adds this to β_(mn) ⁽¹⁾, thereby calculatingβ_(n) ⁽¹⁾, and the process control moves to the next column processingby the switch 45.

The flow of the processing in the “Serial cyclic approximated minalgorithm” according to the present embodiment is explained next withreference to a flowchart shown in FIG. 9. In FIG. 9, it is describedthat the “row processing”, “column processing”, “row processing”, . . ., “column processing” are performed in the “iterative decoding firsttime”, “iterative decoding second time”, . . . , “iterative decodinglast time”. In the present embodiment, after the “row processing step1”, the “column processing step” and the “row processing step 2” arerepeated until the calculation is completed for all m of the columnnumber n. That is, the processing is performed in the order of the “rowprocessing step 1”, “column processing step”, “row processing step 2”,“column processing step”, “row processing step 2”, “column processingstep”, . . . , “row processing step 2”, “row processing step 1”, “columnprocessing step”, “row processing step 2”, “column processing step”,“row processing step 2”, “column processing step”, . . . , “rowprocessing step 2”.

In the above “Serial cyclic approximated min algorithm”, thereception-LLR calculating unit 11 first calculates the reception LLRfrom the reception information (steps S11, S12), and sets a result ofthe calculation to the intermediate-result retaining unit 21, as aninitial value (step S13). The controller 25 initializes the number ofrepetitions as l=1 (step S13). The calculation of Equation (33) iscyclically performed from n=1 to n=N, using the λ adding unit 42, theminimum-k-value comparing unit 43, and the sign calculating unit 44, outof the column processing unit 23 (step S13).

Next, the decoding core unit 12 performs the first-time (first-time tothe last-time) iterative decoding calculation (step S14). Specifically,as the first-time iterative decoding, the row processing unit 22performs the row processing (using the reception LLR) to the row having“1” in the first column, and delivers a result of the calculation to thecolumn processing unit 23. Thereafter, the column processing unit 23performs the column processing of the first column, and retains(updates) B_(mn(i)) and S_(m) as a result of the calculation, in theintermediate-result retaining unit 21. Thereafter, the row processingunit 22 executes the row processing step 2, and delivers a result of thecalculation to the column processing unit 23. The row processing unit 22and the column processing unit 23 repeat the column processing step andthe row processing step 2. Thereafter, processing similar to the aboveprocessing is performed in the order of the second column, third column,. . . , N-th column. B_(mn(i)) and S_(m) are retained in theintermediate-result retaining unit 21 (corresponding to the iterativedecoding first time). At the second and subsequent iterative decoding,the row processing is performed using the LLR and S_(m) updated by theprocessing one before. Thereafter, decoding is performed in the similarmanner as in the first time.

After executing the first-time iterative decoding, the decoding-resultdetermining unit 24 performs a hard decision on the posterior valuecalculated at the repetition first time, determines this determinationvalue as the decoding result x′, and performs a parity check (stopregulation). In the stop regulation, when a result of the parity checkis OK (“Hx′=0”) or when the number of repetitions is l=1_(max), thedecoding result x′ at this time is finally output (step S15). When theabove two conditions are not satisfied, the controller 25 sets l=l+1,and the decoding core unit 12 performs the (l+1)-th time iterativedecoding.

Deletion of the memory size according to a notation method of a columnnumber is explained next, as in the embodiment described above. FIG. 10depicts a column number notation according to the present embodiment. Inthe “Serial cyclic approximated min algorithm”, column numbers are notedin the ascending order from n=0, for example. Conventionally, a columnnumber n is expressed as the column number itself (absolute columnnumber) of the parity check matrix. However, in the present embodiment,column numbers are expressed as relative column numbers, such as aminimum column number of “1” of the m-th row in the parity check matrixis expressed as n=0, a column number of the next “1” of the m-th row isexpressed as n=1, and thereafter, the column numbers are expressed asn=2, 3, . . . , at each “1”. That is, conventionally, when the absolutecolumn number of “1” in the parity check matrix is “32768”, the numberof bits necessary to express the column number is 15 bits. On the otherhand, according to the present embodiment, when the row weight is eight,the memory size can be reduced to three bits which can express 0 to 7.When the row weight is 16, the memory size can be reduced to four bitswhich can express 0 to 15.

As described above, in the present embodiment, the LDPC decoding isperformed to minimize the absolute value |β_(mn)| of the LLR for the rowprocessing, to the minimum k value in row unit by the cyclic structure.Therefore, the memory capacity required to store the absolute values canbe substantially reduced. When the row weight is 20 and also k=3, forexample, the required memory capacity can be reduced to 3/20 of theconventional capacity. Further, by changing the column number from theabsolute column number (1, 3, 10, 15 . . . ) to the relative columnnumber (0, 1, 2, 3 . . . ), the required memory capacity can be furtherreduced.

In the “Serial cyclic approximated min algorithm” according to thepresent embodiment, calculation and updating of probability information(LLR) by the row processing and column processing are performedcyclically for each one bit. Accordingly, probability propagation can beperformed more efficiently than that according to the conventional“Min-Sum algorithm”.

In the “Serial cyclic approximated min algorithm” according to thepresent embodiment, as the row processing step 2, α′_(mn) ⁽¹⁾ isupdated. The updated α′_(mn) ⁽¹⁾ is added to β_(mn) ⁽¹⁾ using theupdated result, thereby updating β_(n) ⁽¹⁾. Therefore, the decoding canbe related to the serial decoding in the complete bit unit, and thenumber of repetitions can be further reduced.

In the present embodiment, while the LLR to be row processed has onevalue, the k number can be any number equal to or higher than twovalues. In the present embodiment, it is explained that after the rowprocessing step 1 is performed, the column processing step and the rowprocessing step 2 are performed alternately. The updating of theprobability information (LLR) by the row processing and the columnprocessing is cyclically performed for each one bit. However, theexecution is not limited to the above. Alternatively, calculation andupdating of the probability information (LLR) by the row processing andthe column processing can be performed cyclically for a plurality ofbits each time.

Seventh Embodiment

A receiving device and a decoding method according to a seventhembodiment are explained next. The LDPC decoding according to thepresent embodiment can be applied when the calculation and updating ofthe probability information (LLR) by the row processing and columnprocessing are performed for each one bit or a predetermined pluralityof bits. For example, the number of repetitions can be reduced byparallelizing calculations. In the present embodiment, the “Serialcyclic approximated min algorithm” is executed using what is called“Overlapped” B_(mn) ^(C) and S_(m), by arranging such that the B_(mn(i))and S_(m) of the intermediate-result retaining unit are one setregardless of the number of parallelization, and parallelized allprocessing units update the same B_(mn) ^(C) and S_(m). The decodingalgorithm according to the present embodiment is hereinafter called the“Overlapped serial cyclic approximated min algorithm”.

The “Overlapped serial cyclic approximated min algorithm” executed bythe receiving device according to the present embodiment is shown below.

(Initialization Step)

First, the number of repetitions l=1 and the maximum number ofrepetitions l_(max) are set. Further, a reception LLR: λ_(n) is input,and B_(mn(i)) ^(C) is obtained as given by the following Equation (37),where β_(mn(i)) ⁽⁰⁾ is an LLR of the minimum k value of the m-th row atthe initial time. As a sign of the LLR: β_(mn) ⁽⁰⁾ in the m-th row atthe initial time, sgn(λ_(n)) is input, and S_(m) is obtained as shown bythe following Equation (37):

$\begin{matrix}\text{[Expression~~33]} & \; \\{{{B_{{mn}^{\prime}}^{C} = {{\beta_{{mn}{(i)}}^{(0)}} = {\min\limits_{n \in {{N{(m)}}\backslash \; {\{{{n{(1)}},{n{(2)}},\; \ldots \;,{n{({i - 1})}}}\}}}}\left\lbrack {\lambda_{n}} \right\rbrack}}},{\forall{i \in \left\lbrack {1,k} \right\rbrack}}}{S_{m} = {\prod\limits_{n \in {N{(m)}}}{{sgn}\left( \lambda_{n} \right)}}}{{n(i)} = {\arg \; {\min\limits_{n \in {{N{(m)}}\backslash \; {\{{{n{(1)}},{n{(2)}},\; \ldots \;,{n{({i - 1})}}}\}}}}\left\lbrack {\lambda_{n}} \right\rbrack}}}{{n(0)} = \varphi}} & (37)\end{matrix}$

where B_(mn(i)) ^(C) is an absolute value of the LLR: β_(mn(i)) of theminimum k value of the m-th row, and is used in common in the parallelprocessing, n(i) is a column number of the minimum i-th LLR in B_(mn(i))^(C).

(Row Processing Step 1)

In the present embodiment, a starting column of each row processing isarbitrary. At the stage where the processing ends up to the finalcolumn, decoding is performed again cyclically from the first column. Asthe row processing, the repetition first-time LLR: α_(mn) ⁽¹⁾ of the bitn to be sent from the check node m to the bit node n is updated for0≦g≦G−1, g·N_(G)+1≦n≦(g+1)·N_(G), where G is a parallel number, N_(G) isa column number that each parallelized decoding circuit processes, andG·N_(g)=N, and for each m, by the following Equation (38):

$\begin{matrix}\text{[Expression~~34]} & \; \\{\begin{matrix}{\alpha_{mn}^{(l)} = {\prod\limits_{\underset{n^{\prime} < {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}\backslash \; n}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(l)} \right)} \cdot}}} \\{{\prod\limits_{\underset{n^{\prime} < {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}\backslash \; n}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lfloor B_{{mn}^{\prime}}^{C} \right\rfloor}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}\end{matrix}{S_{m}^{\prime} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)}}}{\beta_{n}^{(l)} = {\lambda_{n} + {\sum\limits_{m \in {M{(n)}}}\alpha_{mn}^{(l)}}}}} & (38)\end{matrix}$

Specifically, for example, G row processing units allocated to the Gcolumns, into which the column is divided for each column number: N_(G),perform the row processing in parallel. The G row processing unitsperform the parallel processing, and perform the same operation as thatof the “Serial cyclic approximated min algorithm”, except that all theprocessing units use the same B_(mn) ^(C).

(Column Processing Step)

Next, as the column processing, the repetition first-time LLR: β_(mn)⁽¹⁾ of the bit n to be sent from the bit node n to the check node m isupdated, for each m of the column number n performed at the rowprocessing step 1, by the following Equation (39). That is, in thepresent embodiment, the column processing represented by the followingEquation (39) is performed in parallel, for each column after the rowprocessing is performed in parallel as described above. However, inperforming the column processing in parallel, at the subsequent columnprocessing step and the row processing step 2, the calculation isperformed for each row in order starting from the smallest row number ofthe row number m, for example. However, when all rows having “1”standing are executed without overlapping the order of the row numbersto be executed, the calculation can be performed in any order.

$\begin{matrix}\text{[Expression~~35]} & \; \\{{\beta_{mn}^{(l)} = {{\lambda_{n} + {\sum\limits_{m^{\prime} \in {{M{(m)}}\backslash \; m}}\alpha_{m^{\prime}n}^{\prime {(l)}}}} = {\beta_{n}^{(l)} - \alpha_{mn}^{(l)}}}}{S_{m} = {S_{m}^{\prime} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)}}}{{n_{i} = {\arg \; {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash {\{{n_{1},n_{2},\; \ldots \;,n_{i - 1},n_{i},n}\}}}}\left\lbrack {B_{{mn}^{\prime}}^{C},{\beta_{mn}^{(l)}}} \right\rbrack}}},{B_{{mn}_{i}} = {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; {\{{n_{1},n_{2},\; \ldots \;,n_{i - 1},n_{i},n}\}}}}\left\lbrack {B_{{mn}^{\prime}}^{C},{\beta_{mn}^{(l)}}} \right\rbrack}},{\forall{i \in \left\lbrack {1,k} \right\rbrack}}}} & (39)\end{matrix}$

(Row Processing Step 2)

Further, as the row processing again, the repetition first-time LLR:α′_(mn) ⁽¹⁾ of the bit n to be sent from the check node m to the bitnode n is updated, for the same m of the row executed in the columnprocessing of the column number n, by the following Equation (40):

$\begin{matrix}\text{[Expression~~36]} & \; \\{{\alpha_{mn}^{\prime {(l)}} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lfloor B_{{mn}^{\prime}}^{C} \right\rfloor}}}{S_{m}^{\prime} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)}}}{\beta_{n}^{(l)} = {\beta_{mn}^{(l)} + \alpha_{mn}^{\prime {(l)}}}}} & (40)\end{matrix}$

Specifically, as the row processing again, α′_(mn) ⁽¹⁾ is updated. Theupdated α′_(mn) ⁽¹⁾ is added to β_(mn) ⁽¹⁾ using the updated result,thereby updating β_(n) ⁽¹⁾. Thereafter, by returning to the columnprocessing step, calculation is repeated until when the calculation iscompleted for all m of the column number n. When the processes at thecolumn processing step and the row processing step end for all rows mhaving “1” standing in the check matrix of the column number n, theprocess control moves to the stop regulation.

The stop regulation is similar to that of the “Serial cyclicapproximated min algorithm” described above.

A configuration and operation of the LDPC decoder 5 according to theseventh embodiment that achieves the above “Overlapped serial cyclicapproximated min algorithm” is explained below.

FIG. 13 is a configuration example of the LDPC decoder 5 according tothe present embodiment, which is similar to the configuration of theembodiment described above. This LDPC decoder 5 includes thereception-LLR calculating unit 11 that calculates the reception LLR fromthe reception information, and the decoding core unit 12 a that performsdecoding of the present embodiment. The decoding core unit 12 a includesthe intermediate-result retaining unit 21 a configured by a memory whichstores therein an intermediate result (intermediate value) of decoding,the row processing units 22-1 to 22-G that perform row processing(parallel processing) according to the present embodiment, the columnprocessing units 23-1 to 23-G that execute column processing (parallelprocessing) according to the present embodiment, the decoding-resultdetermining unit 24 that performs a hard decision of a posterior valuein the column processing and an error determination of a parity checkresult, as a stop regulation according to the present embodiment, andthe controller 25 a that performs a repetition control of decoding.

In FIG. 13, the LDPC decoder 5 according to the present embodiment usesin common B_(mn) ^(C) and S_(m) of the intermediate-result retainingunit 21 a, following the above Equations (37), (38), (39), and (40),when each row processing unit and each column processing unit performprocessing in parallel, thereby updating B_(mn) ^(C) and S_(m),respectively. Based on this parallel processing, B_(mn) ^(C) and S_(m)are rapidly updated according to the parallel number, whichsubstantially reduces the number of iterative decodings.

According to the present embodiment, in the parallel processing, whencalculation of the same row occurs in the same clock and when the samebuffer is referenced, various measures are taken, such as a memoryaccess priority order is set to each processing unit, a memory bank ispartitioned, and the timing of the memory access is adjusted using ashift register.

As described above, in the “Overlapped serial cyclic approximated minalgorithm” according to the present embodiment, the row processing andthe column processing are performed in parallel, using the “Serialcyclic approximated min algorithm” described above. Further, theintermediate-result retaining unit that retains the minimum k valueupdated in each column processing performed in parallel is shared, andthe minimum k value is updated in each column processing performed inparallel. With this arrangement, the decoding number of repetitions canbe substantially reduced, as compared with the decrease according to the“Min-Sum algorithm” and the above sixth embodiment.

In the “Overlapped serial cyclic approximated min algorithm” accordingto the present embodiment, as the row processing step 2, α′_(mn) ⁽¹⁾ isupdated, and the updated α′_(mn) ⁽¹⁾ is added to β_(mn) ⁽¹⁾ using theupdated result, thereby updating β_(n) ⁽¹⁾. Therefore, the decoding canbe related to the serial decoding in the complete bit unit, and thenumber of repetitions can be further reduced, as compared with thedecrease in the second embodiment.

Eighth Embodiment

A receiving device (communication apparatus) and a decoding methodaccording to an eighth embodiment are explained below. In the presentembodiment, the process of updating only the absolute value of the LLRof the minimum k value and the decoding using the approximate minimumvalue in the “Serial cyclic approximated min algorithm” according to thesixth embodiment or the “Overlapped serial cyclic approximated minalgorithm” according to the seventh embodiment are cyclically applied tothe “Normalized BP-based algorithm” as the known decoding algorithmusing the “Min-Sum algorithm”.

Before explaining the decoding algorithm of the present embodiment, theknown “Normalized BP-based algorithm” that is the basis of the decodingalgorithm is shown below. The row processing different from that of the“Min-Sum algorithm” is explained.

(Row Processing Step 1)

A row processing step 1 of the “Normalized BP-based algorithm” can begeneralized by the following Equation (41). In this case, as the rowprocessing step 1, the repetition first-time LLR: α_(mn) ⁽¹⁾ is updatedfor each of m and n by the following Equation (41), where A is aconstant called a normalization factor. In the “Normalized BP-basedalgorithm”, the repetition first-time LLR obtained by the “Min-Sumalgorithm” is corrected by the normalization factor A.

$\begin{matrix}\text{[Expression~~37]} & \; \\\begin{matrix}{\alpha_{mn}^{(1)} = {2{\tanh^{- 1}\left( {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{\tanh\left( \frac{\beta_{{mn}^{\prime}}^{({l - 1})}}{2} \right)}} \right)}}} \\{= {2{\tanh^{- 1}\left( {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{\tanh\left( \frac{\beta_{{mn}^{\prime}}^{({l - 1})}}{2} \right)}}}} \right)}}} \\{= {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot 2}{\tanh^{- 1}\left( {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{\tanh\left( \frac{\beta_{{mn}^{\prime}}^{({l - 1})}}{2} \right)}} \right)}}}} \\{\approx {\frac{1}{A}{\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{\beta_{{mn}^{\prime}}^{({l - 1})}}}}}}}\end{matrix} & (41)\end{matrix}$

The decoding algorithm when the “Serial cyclic approximated minalgorithm” or the “Overlapped serial cyclic approximated min algorithm”is applied to the “Normalized BP-based algorithm” is explained below. Inthe following, explanations are omitted for the processing(initialization, column processing, and stop regulation) similar to thatof the “Serial cyclic approximated min algorithm” or the “Overlappedserial cyclic approximated min algorithm”. The row processing step 1different from that of the “Serial cyclic approximated min algorithm” orthe “Overlapped serial cyclic approximated min algorithm” is explainedbelow.

(Row Processing Step 1 Using Serial Cyclic Approximated min Algorithm)

In the present embodiment, a starting column of the row processing isarbitrary. At the stage where the processing ends to the last column,decoding is performed again cyclically from the first column. The α_(mn)⁽¹⁾ and α′_(mn) ⁽¹⁾ of the row processing steps 1 and 2 of the decodingalgorithm according to the present embodiment using the “Serial cyclicapproximated min algorithm” can be generalized by the following Equation(42). In this case, as the row processing step 1, the repetitionfirst-time LLR: α_(mn) ⁽¹⁾ is updated for each of m and n by thefollowing Equation (42). That is, the repetition first-time LLR obtainedby the “Serial cyclic approximated min algorithm” is corrected by thenormalization factor A in the following Equation (42):

$\begin{matrix}\text{[Expression~~38]} & \; \\{\begin{matrix}{\alpha_{mn}^{(l)} = {\frac{1}{A}{\prod\limits_{\underset{n^{\prime} < n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(l)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}}}}} \\{= {\frac{1}{A}{S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}} \\{= {\frac{1}{A}{S_{m}^{\prime} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\left\lbrack B_{{mn}^{\prime}} \right\rbrack.}}}}}\end{matrix}{\alpha_{mn}^{\prime {(l)}} = {\frac{1}{A}{S_{m} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}}} & (42)\end{matrix}$

(Row Processing Step 1 Using Overlapped Serial Cyclic Approximated minAlgorithm)

The α_(mn) ⁽¹⁾ and α′_(mn) ⁽¹⁾ of the row processing steps 1 and 2 ofthe decoding algorithm according to the present embodiment using the“Overlapped serial cyclic approximated min algorithm” can be generalizedby the following Equation (43). In this case, as the row processing step1, the repetition first-time LLR: α_(mn) ⁽¹⁾ is updated for 0≦g≦G−1,g·N_(G)+1≦n≦(g+1)·N_(G), and for each m by the following Equation (43).That is, in the following Equation (43), the repetition first-time LLRobtained by the “Overlapped serial cyclic approximated min algorithm” iscorrected by the normalization factor A.

$\begin{matrix}\text{[Expression~~39]} & \; \\{\begin{matrix}{\alpha_{mn}^{(l)} = {\frac{1}{A}{\prod\limits_{\underset{n^{\prime} < {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}\backslash \; n}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(l)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}\backslash \; n}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}}}}} \\{= {\frac{1}{A}{S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}} \\{= {\frac{1}{A}{S_{m}^{\prime} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}}\end{matrix}{\alpha_{mn}^{\prime {(l)}} = {\frac{1}{A}{S_{m} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)} \cdot {\min\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}}} & (43)\end{matrix}$

In the decoding algorithm according to the present embodiment, after therow processing step 1 is performed as described above, processing basedon the column processing and the stop regulation similar to those of the“Serial cyclic approximated min algorithm” or the “Overlapped serialcyclic approximated min algorithm” is performed to obtain the final coderesult.

Characteristic operations of the row processing unit of the LDPC decoder5 that executes the decoding algorithm of the present embodiment areexplained below with reference to the drawings. The entire configurationof the LDPC decoder 5 is similar to that shown in FIG. 5 or FIG. 13.

FIG. 15 is a configuration example of the row processing units 22, 22-1to 22-G that perform row processing of the present embodiment, which issimilar to the example of the above embodiments. The row processing unitincludes the minimum value selecting unit 31 a. Configurations similarto those explained with reference to FIG. 6 are denoted by likereference numerals, and explanations thereof are not repeated. Theminimum value selecting unit 31 a according to the present embodimentcorrects the minimum value (Min 1LLR or Min 2LLR) of the LLR read fromthe intermediate-result retaining unit 21 (or 21 a), using thenormalization factor A, for example. Specifically, the minimum valueselecting unit 31 a performs the normalization by dividing the LLRminimum value by A.

As described above, according to the present embodiment, the “Serialcyclic approximated min algorithm” or the “Overlapped serial cyclicapproximated min algorithm” is applied to the “Normalized BP-basedalgorithm” having the better performance than that of the “Min-Sumalgorithm”. With this arrangement, effects similar to those of the sixthand seventh embodiments can be obtained. Further, performance close tothat of the “Sum-Product algorithm” can be achieved, regardless of thecircuit amount substantially equivalent to that of the “Min-Sumalgorithm”.

In the present embodiment, the “Serial cyclic approximated minalgorithm” or the “Overlapped serial cyclic approximated min algorithm”is applied to the “Normalized BP-based algorithm”. Alternatively, the“Serial cyclic approximated min algorithm” or the “Overlapped serialcyclic approximated min algorithm” can also be applied to the known“Offset BP-based algorithm” or other algorithm. In this case, effectssimilar to those described above can also be obtained.

Ninth Embodiment

A receiving device (communication apparatus) and a decoding methodaccording to a ninth embodiment are explained below. In the presentembodiment, the process of updating only the absolute value of the LLRof the minimum k value and the decoding using the approximate minimumvalue in the “Serial cyclic approximated min algorithm” according to thesixth embodiment or the “Overlapped serial cyclic approximated minalgorithm” according to the seventh embodiment are cyclically applied tothe “δ min algorithm” as the known decoding algorithm having superiorcorrection performance of LLR: β_(mn) to that of the “NormalizedBP-based algorithm” or the “Offset BP-based algorithm”.

Before explaining the decoding algorithm of the present embodiment, theknown “δ min algorithm” that is the basis of the decoding algorithm isexplained. The row processing different from that of the “Min-Sumalgorithm” is explained below.

(Row Processing Step 1)

The α_(mn) ⁽¹⁾ and α′_(mn) ⁽¹⁾ of the row processing steps 1 and 2 ofthe “δ min algorithm” can be generalized by the following Equation (44).In this case, as the row processing step 1, the repetition first-timeLLR: α_(mn) ⁽¹⁾ is updated for each of m and n by the following Equation(44). At the row processing step 1 of the “δ min algorithm”, α_(mn) ⁽¹⁾is calculated by calculating Θ from the absolute value: |β_(mn′)^((i−1))| of the LLR updated at the repetition l−1-th time.

$\begin{matrix}\text{[Expression~~40]} & \; \\{{{\alpha_{m,n}^{(i)} = {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({i - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N{(m)}}\backslash \; n}}{\Theta}\left\lbrack {\beta_{m,n^{\prime}}^{({i - 1})}} \right\rbrack}}}}{\underset{n \in A}{\Theta}\left( I_{n} \right)} \equiv {I_{1}\Theta \; I_{2}\Theta \mspace{14mu} \ldots \mspace{14mu} \Theta \; I_{A}}}{{a\; \Theta \; b} \equiv {\max \left( {{{\min \left( {a,b} \right)} - \Delta},0} \right)}}{\Delta \equiv {\max \left( {{0.9 - {{{a - b}}/2}},0} \right)}}{\alpha_{m,n}^{\prime {(l)}} = {\prod\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(l)} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Theta}\left\lbrack \beta_{{mn}^{\prime}} \right\rbrack}}}}} & (44)\end{matrix}$

The decoding algorithm when the “Serial cyclic approximated minalgorithm” or the “Overlapped serial cyclic approximated min algorithm”is applied to the “δ min algorithm” is explained below. In thefollowing, explanations are omitted for the processing (initialization,column processing, and stop regulation) similar to that of the “Serialcyclic approximated min algorithm” or the “Overlapped serial cyclicapproximated min algorithm”. The row processing step 1 different fromthat of the “Serial cyclic approximated min algorithm” or the“Overlapped serial cyclic approximated min algorithm” is explainedbelow. In the present embodiment, a starting column of the rowprocessing is arbitrary. At the stage where the processing ends to thelast column, decoding is performed again cyclically from the firstcolumn.

(Row Processing Step 1 Using Serial Cyclic Approximated min Algorithm)

The α_(mn) ⁽¹⁾ and α′_(mn) ⁽¹⁾ of the row processing steps 1 and 2 ofthe decoding algorithm of the present embodiment using the “Serialcyclic approximated min algorithm” can be generalized by the followingEquation (45). In this case, as the row processing step 1, therepetition first-time LLR: α_(mn) ⁽¹⁾ is updated for 1≦n≦N and for eachm by the following Equation (45). In the row processing step 1 of thedecoding algorithm, α_(mn) ⁽¹⁾ is calculated by calculating Θ from theabsolute value: B_(mn′) of the LLR of the minimum k value updated at therepetition l−1-th time.

$\begin{matrix}\text{[Expression~~41]} & \; \\{\begin{matrix}{\alpha_{mn}^{(l)} = {\prod\limits_{\underset{n^{\prime} < n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(l)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}\end{matrix}{\alpha_{m,n}^{\prime {(l)}} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Theta}\left\lbrack \beta_{{mn}^{\prime}} \right\rbrack}}}} & (45)\end{matrix}$

(Row Processing Step 1 Using Overlapped Serial Cyclic Approximated minAlgorithm)

The α_(mn) ⁽¹⁾ and α′_(mn) ⁽¹⁾ of the row processing steps 1 and 2 ofthe decoding algorithm of the present embodiment using the “Overlappedserial cyclic approximated min algorithm” can be generalized by thefollowing Equation (46). In this case, as the row processing step 1, therepetition first-time LLR: α_(mn) ⁽¹⁾ is updated for 0≦g≦G−1,g·N_(G)+1≦n≦(g+1)·N_(G), and for each m by the following Equation (46).At the row processing step 1 of this decoding algorithm, α_(mn) ⁽¹⁾ iscalculated by calculating Θ from the absolute value: B_(mn′) ^(C) of theLLR of the minimum k value updated by the parallel processing at therepetition l−1-th time.

$\begin{matrix}\text{[Expression~~42]} & \; \\{\begin{matrix}{\alpha_{mn}^{(l)} = {\prod\limits_{\underset{n^{\prime} < {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}\backslash \; n}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(l)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}\backslash \; n}}}{{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot \underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Theta}}\left\lfloor B_{{mn}^{\prime}}^{C} \right\rfloor}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Theta}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Theta}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}\end{matrix}{\alpha_{mn}^{\prime {(l)}} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Theta}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}} & (46)\end{matrix}$

In the decoding algorithm according to the present embodiment, after therow processing step 1 is performed as described above, processing basedon the column processing, the row processing step 2, and the stopregulation similar to those of the “Serial cyclic approximated minalgorithm” or the “Overlapped serial cyclic approximated min algorithm”is executed, thereby obtaining the final code result.

Characteristic operations of the row processing unit of the LDPC decoder5 that executes the decoding algorithm of the present embodiment areexplained below with reference to the drawings. The entire configurationof the LDPC decoder 5 is similar to that shown in FIG. 5 or FIG. 13.

FIG. 16 is a configuration example of the row processing units 22, 22-1to 22-G that perform row processing of the present embodiment, which issimilar to that described in the above embodiments. This row processingunit includes the minimum-value selecting unit 31 b. Constituentelements similar to those described with reference to FIG. 6 are denotedby like reference numerals, and explanations thereof are not repeated.While the LDPC decoder 5 shown in FIG. 5 is explained as one example,the present embodiment can also be similarly applied to the LDPC decoder5 shown in FIG. 13.

The minimum-value selecting unit 31 b according to the presentembodiment reads the Min 1LLR(B_(mn(1))), Min 2LLR(B_(mn(2))), MinkLLR(B_(mn(k))), and their column numbers from the intermediate-resultretaining unit 21, and the calculating unit performs the Θ calculation.That is, in the minimum-value selecting unit 31 b according to thepresent embodiment, the calculating unit performs the followingcalculation in the “δ min algorithm”, to B_(mn(k)) in which the n-thcolumn to be processed does not coincide with the column number n(k) ofB_(mn(k)) retained in the intermediate-result retaining unit 21.

For example, the calculating unit obtains the updated value |α_(mn)⁽¹⁾|(=Θ[(B_(mn′)]) excluding the sign as represented by the followingEquation (47):

$\begin{matrix}\text{[Expression~~43]} & \; \\{\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack} & (47)\end{matrix}$

Further, by limiting the LLR to be calculated from the k value to theminimum 3 values, the calculations can be reduced. The calculating unitobtains the updated value |α_(mn) ⁽¹⁾|(=Θ[(B_(mn′)]) excluding the signas represented by the following Equation (48):

$\begin{matrix}\text{[Expression~~44]} & \; \\{{{{if}\mspace{14mu} \left( {n = n_{(1)}} \right){\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {B_{{mn}_{(2)}}\Theta \; B_{{mn}_{(3)}}}}{{{else}\mspace{14mu} {if}\mspace{14mu} \left( {n = n_{(2)}} \right){\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {B_{{mn}_{(1)}}\Theta \; B_{{mn}_{(3)}}}}{{{else}\mspace{14mu} {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Theta}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {B_{{mn}_{(1)}}\Theta \; B_{{mn}_{(2)}}}}} & (48)\end{matrix}$

While the LLR to be calculated is limited from the k value to theminimum 3 values in the above example, the embodiment can also beapplied to the case that the LLR is limited to the minimum 4, 5, . . .values.

As described above, according to the present embodiment, the “Serialcyclic approximated min algorithm” or the “Overlapped serial cyclicapproximated min algorithm” is applied to the “δ min algorithm” havingthe better performance than that of the “Min-Sum algorithm”. With thisarrangement, effects similar to those of the sixth and seventhembodiments can be obtained. Further, performance close to that of the“Sum-Product algorithm” can be achieved, regardless of the circuitamount substantially equivalent to that of the “Min-Sum algorithm”. Inthe present embodiment, description is made for the case that theminimum value of the absolute values of the LLR for the row processingis corrected to the optimum value based on a predetermined correctionequation prescribed by the known “δ min algorithm”. However, thecorrection equation is not limited to this, and the correction equationprescribed by the algorithm other than the “δ min algorithm” can also beused. In this case, effects similar to those described above can also beobtained.

Tenth Embodiment

A receiving device (communication apparatus) and a decoding methodaccording to a tenth embodiment are explained below. In the presentembodiment, the process of updating only the absolute value of the LLRof the minimum k value and the decoding using the approximate minimumvalue in the “Serial cyclic approximated min algorithm” according to thesixth embodiment or the “Overlapped serial cyclic approximated minalgorithm” according to the seventh embodiment are cyclically applied tothe “Sum-Product algorithm”.

Before explaining the decoding algorithm of the present embodiment, theknown “Sum-Product algorithm” that is the basis of the decodingalgorithm is explained. In the present embodiment, a method ofcalculation by tabling the mathematical function, i.e., a general“Sum-Product algorithm” using a TLU (table lookup), is described. Therow processing different from that of the “Sum-Product algorithm”explained in the conventional technology is described.

(Row Processing Step 1 (1))

The α_(mn) ⁽¹⁾ and α′_(mn) ⁽¹⁾ of the row processing steps 1 and 2 ofthe “Sum-Product algorithm” using a TLU can be generalized by thefollowing Equation (49). In this case, as the row processing step 1, therepetition first-time LLR: α_(mn) ⁽¹⁾ is updated for each of m and n bythe following Equation (49). In the row processing step 1 of the“Sum-Product algorithm” using the TLU, a calculation using the TLU isperformed to the absolute value: |β_(mn′) ^((l−1))| of the LLR updatedat the repetition l−1-th time.

$\begin{matrix}\text{[Expression~~45]} & \; \\{{\alpha_{m,n}^{(i)} = {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({i - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N{(m)}}\backslash \; n}}{TLU}\left\lbrack {\beta_{m,n}^{({i - 1})}} \right\rbrack}}}}{{\underset{n \in A}{TLU}\left( I_{n} \right)} \equiv {{TLU}\left( {I_{1},{{TLU}\left( {I_{2},{\ldots \mspace{11mu} {{TLU}\left( {I_{{A} - 1},I_{A}} \right)}}} \right)}} \right)}}{{{TLU}\left( {a,b} \right)} \equiv {2{\tanh^{- 1}\left( {\tanh \; {\frac{a}{2} \cdot \tanh}\; \frac{b}{2}} \right)}}}{\alpha_{mn}^{\prime {(l)}} = {\prod\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{{{sgn}\left( \beta_{mn}^{(l)} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack \beta_{{mn}^{\prime}}^{(l)} \right\rbrack}}}}} & (49)\end{matrix}$

(Row Processing Step 1 (2))

The row processing step 1 of the “Sum-Product algorithm” using the TLUcan also be achieved by the method different from the above method. Forexample, the α_(mn) ⁽¹⁾ and α′_(mn) ⁽¹⁾ of the row processing steps 1and 2 of the “Sum-Product algorithm” using a TLU different from theabove algorithm can be generalized by the following Equation (50). Inthis case, as the row processing step 1, the repetition first-time LLR:α_(mn) ⁽¹⁾ is updated for each of m and n by the following Equation(50):

$\begin{matrix}\text{[Expression~~46]} & \; \\{{\alpha_{m,n}^{(i)} = {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({i - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N{(m)}}\backslash \; n}}{\Xi}\left\lbrack {\beta_{m,n^{\prime}}^{({i - 1})}} \right\rbrack}}}}{{\underset{n \in A}{\Xi}\left( I_{n} \right)} \equiv {I_{1}\Xi \; I_{2}\Theta \mspace{11mu} \ldots \mspace{11mu} \Xi \; I_{A}}}{{a\; \Xi \; b} \equiv {{\min \left( {a,b} \right)} + {{TLU}\; 1\left( {{a + b}} \right)} - {{TLU}\; 1\left( {{a - b}} \right)}}}{a_{mn}^{\prime {(l)}} = {\prod\limits_{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{{{sgn}\left( \beta_{mn}^{(l)} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack \beta_{{mn}^{\prime}}^{(l)} \right\rbrack}}}}} & (50)\end{matrix}$

For the TLU1(x), a table is prepared in advance based on the following(51).

TLU1(x)=ln(1+exp(−x))  (51)

In the “Sum-Product algorithm” using the TLU, the row processing step 1represented by the above Equation (49) has a characteristic that whilethe table becomes large, the number of calculations is small. On theother hand, the row processing step 1 represented by the above Equation(50) has a characteristic that the number of calculations is largealthough the table becomes small.

The decoding algorithm when the “Serial cyclic approximated minalgorithm” is applied to the “Sum-Product algorithm” using the TLU isexplained below. In the following, explanations are omitted for theprocessing (initialization, column processing, and stop regulation)similar to that of the “Serial cyclic approximated min algorithm”. Therow processing step 1 different from that of the “Serial cyclicapproximated min algorithm” is explained below. In the presentembodiment, a starting column of the row processing is arbitrary, and atthe stage where the processing ends up to the final column, decoding isperformed again cyclically from the first column.

(Row Processing Step 1 (1) Using Serial Cyclic Approximated minAlgorithm)

The α_(mn) ⁽¹⁾ and α′_(mn) ⁽¹⁾ of the row processing steps 1 and 2 ofthe decoding algorithm according to the present embodiment having the“Serial cyclic approximated min algorithm” applied to the row processingstep (1) can be generalized by the following Equation (52). In thiscase, as the row processing step 1, the repetition first-time LLR:α_(mn) ⁽¹⁾ is updated for 1≦n≦N and for each m by the following Equation(52). In the row processing step 1 of the decoding algorithm, acalculation using the TLU is performed to the absolute value: B_(mn′) ofthe LLR of the minimum k value updated at the repetition l−1-th time.

$\begin{matrix}\text{[Expression~~47]} & \; \\{\begin{matrix}{\alpha_{mn}^{(l)} = {\prod\limits_{\underset{n^{\prime} < n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(l)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}\end{matrix}{\alpha_{mn}^{\prime {(l)}} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}} & (52)\end{matrix}$

(Row Processing Step Using Serial Cyclic Approximated min Algorithm 1(2))

The α_(mn) ⁽¹⁾ and α′_(mn) ⁽¹⁾ of the row processing steps 1 and 2 ofthe decoding algorithm according to the present embodiment having the“Serial cyclic approximated min algorithm” applied to the row processingstep 1(2) can be generalized by the following Equation (53). In thiscase, as the row processing step 1, the repetition first-time LLR:α_(mn) ⁽¹⁾ is updated for 1≦n≦N and for each m by the following Equation(53):

$\begin{matrix}\text{[Expression~~48]} & \; \\{\begin{matrix}{\alpha_{mn}^{(l)} = {\prod\limits_{\underset{n^{\prime} < n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(l)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > n}{n^{\prime} \in N}{{(m)}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}\end{matrix}{\alpha_{mn}^{\prime {(l)}} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}}}} & (53)\end{matrix}$

The decoding algorithm when the “Overlapped serial cyclic approximatedmin algorithm” is applied to the “Sum-Product algorithm” using the TLUis explained below. In the following, explanations are omitted for theprocessing (initialization, column processing, and stop regulation)similar to that of the “Overlapped serial cyclic approximated minalgorithm”. The row processing step 1 different from that of the“Overlapped serial cyclic approximated min algorithm” is explainedbelow.

(Row Processing Step Using Overlapped Serial Cyclic Approximated minAlgorithm 1(1))

The α_(mn) ⁽¹⁾ and α′_(mn) ⁽¹⁾ of the row processing steps 1 and 2 ofthe decoding algorithm according to the present embodiment having the“Overlapped serial cyclic approximated min algorithm” applied to the rowprocessing step 1(1) can be generalized by the following Equation (54).In this case, as the row processing step 1, the repetition first-timeLLR: α_(mn) ⁽¹⁾ is updated for 0≦g≦G−1, g·N_(G)+1≦n≦(g+1)·N_(G), and foreach m by the following Equation (54). In the row processing step 1 ofthis decoding algorithm, a calculation using the TLU is performed to theabsolute value: B_(mn′) ^(C) of the LLR of the minimum k value updatedby the parallel processing at the repetition l−1-th time.

$\begin{matrix}\text{[Expression~~49]} & \; \\{\begin{matrix}{\alpha_{mn}^{(l)} = {\prod\limits_{\underset{n^{\prime} < {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}\backslash \; n}}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(l)} \right)} \cdot {\prod\limits_{\underset{n^{\prime} > {g \cdot N_{G}}}{n^{\prime} \in {{N{(m)}}\backslash \; n}}}{{\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right) \cdot \underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}}\left\lfloor B_{{mn}^{\prime}}^{C} \right\rfloor}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}\end{matrix}{\alpha_{mn}^{\prime} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}} & (54)\end{matrix}$

(Row Processing Step Using Overlapped Serial Cyclic Approximated minAlgorithm 1(2))

The α_(mn) ⁽¹⁾ and α′_(mn) ⁽¹⁾ of the row processing steps 1 and 2 ofthe decoding algorithm according to the present embodiment having the“Overlapped serial cyclic approximated min algorithm” applied to the rowprocessing step 1(2) can be generalized by the following Equation (55).In this case, as the row processing step 1, the repetition first-timeLLR: α_(mn) ⁽¹⁾ is updated for 0≦g≦G−1, g·N_(G)+1≦n≦(g+1)·N_(G), and foreach m by the following Equation (55):

$\begin{matrix}\text{[Expression~~50]} & \; \\{\begin{matrix}{\alpha_{mn}^{(l)} = {\prod\limits_{\underset{n^{\prime} < {g \cdot N_{G}}}{n^{\prime} \in {N{(m)}}}\backslash \; n}{{{sgn}\left( \beta_{{mn}^{\prime}}^{(l)} \right)} \cdot {\prod\limits_{n^{\prime} \in {{N{(m)}}\backslash \; n}}{{{sgn}\left( \beta_{{mn}^{\prime}}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}}}} \\{= {S_{m} \cdot {{sgn}\left( \beta_{mn}^{({l - 1})} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}} \\{= {S_{m}^{\prime} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}\end{matrix}{\alpha_{mn}^{\prime {(l)}} = {S_{m} \cdot {{sgn}\left( \beta_{mn}^{(l)} \right)} \cdot {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}}^{C} \right\rbrack}}}} & (55)\end{matrix}$

Characteristic operations of the row processing unit of the LDPC decoder5 that executes the decoding algorithm of the present embodiment areexplained below with reference to the drawings. The entire configurationof the LDPC decoder 5 is similar to that shown in FIG. 5 or FIG. 13.

FIG. 18 is a configuration example of the row processing units 22, 22-1to 22-G that perform row processing of the present embodiment, which issimilar to the configuration of the embodiment described above. The rowprocessing unit includes the minimum-value selecting unit 31 c.Constituent elements similar to those described with reference to FIG. 6are denoted by like reference numerals, and explanations thereof are notrepeated. While the LDPC decoder 5 shown in FIG. 5 is explained as oneexample, the present embodiment can also be similarly applied to theLDPC decoder 5 shown in FIG. 13.

The minimum-value selecting unit 31 c according to the presentembodiment reads the Min 1LLR(B_(mn(1))), Min 2LLR(B_(mn(2))), MinkLLR(B_(mn(k))), and their column numbers from the intermediate-resultretaining unit 21, and the calculating unit performs calculation usingthe TLU. That is, in the minimum-value selecting unit 31 c according tothe present embodiment, the calculating unit performs the followingcalculation in the “Sum-Product min algorithm”, to B_(mn(k)) in whichthe n-th column to be processed does not coincide with the column numbern(k) of B_(mn(k)) retained in the intermediate-result retaining unit 21.

For example, the calculating unit obtains the updated value excludingthe sign, as represented by the following Equation (56):

$\begin{matrix}\text{[Expression~~51]} & \; \\{{\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}\mspace{14mu} {OR}\mspace{14mu} {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} & (56)\end{matrix}$

Further, by limiting the LLR to be calculated from the k value to theminimum 3 values, the calculations can be reduced. The calculating unitobtains the updated value excluding the sign as represented by thefollowing Equation (57):

$\begin{matrix}\text{[Expression~~52]} & \; \\{{{{if}\mspace{14mu} \left( {n = n_{(1)}} \right){\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {{{{TLU}\left( {B_{{mn}_{(2)}},B_{{mn}_{(3)}}} \right)}\mspace{14mu} {OR}\mspace{14mu} {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {B_{{mn}_{(2)}}\Xi \; B_{{mn}_{(3)}}}}}{{{else}\mspace{14mu} {if}\mspace{14mu} \left( {n = n_{(2)}} \right){\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {{{{TLU}\left( {B_{{mn}_{(1)},}B_{{mn}_{(2)}}} \right)}\mspace{14mu} {OR}\mspace{14mu} {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {B_{{mn}_{(1)}}\Xi \; B_{{mn}_{(2)}}}}}{{{else}\mspace{14mu} {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{TLU}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {{{{TLU}\left( {B_{{mn}_{(1)}},B_{{mn}_{(2)}}} \right)}\mspace{14mu} {OR}\mspace{14mu} {\underset{n^{\prime} \in {{N_{k}{(m)}}\backslash \; n}}{\Xi}\left\lbrack B_{{mn}^{\prime}} \right\rbrack}} = {B_{{mn}_{(1)}}\Xi \; B_{{mn}_{(2)}}}}}} & (57)\end{matrix}$

While the LLR to be calculated is limited from the k value to theminimum 3 values in the above example, the embodiment can also beapplied to the case that the LLR is limited to the minimum 4, 5, . . .values.

As described above, according to the present embodiment, the “Serialcyclic approximated min algorithm” or the “Overlapped serial cyclicapproximated min algorithm” is applied to the “Sum-Product algorithm”using the TLU. With this arrangement, although calculations and therequired memory capacity increase as compared with other embodiments,decoding performance can be improved. While the “Sum-Product algorithm”using the TLU is explained in the present embodiment, the principle canbe similarly applied to other decoding algorithm for performing the TLUto the mathematical function. In the present embodiment, the TLUprescribed by the known “Sum-Product algorithm” is used for the minimumvalue of the absolute values of the LLR for the row processing. However,the TLU is not limited to the above, and the TLU other than the TLUprescribed by the “Sum-Product algorithm” can also be used. In thiscase, effects similar to the effects described above can also beobtained.

In the above embodiments, the processing is performed in the ascendingorder with the starting column of the row processing set as 1. However,for example, the starting column can be arbitrary, and the processingcan be performed to an arbitrary column which is not overlapped. At thestage where the processing ends for all columns, iterative decoding canbe performed again in the same order. Alternatively, the starting columnof the row processing can be set arbitrary, and the processing can beperformed to an arbitrary column which is not overlapped. At the stagewhere the processing ends for all columns, iterative decoding can beperformed again in a different order to the arbitrary column notoverlapped until the processing ends for all columns. In these cases,effects similar to those of each of the above embodiments can also beobtained. While the use of the logarithmic likelihood ratio (LLR) as theprobability information is explained in the above embodiments, otherinformation than the logarithmic likelihood ratio (LLR) can also be usedas the probability information.

INDUSTRIAL APPLICABILITY

As described above, the receiving device and the decoding methodaccording to the present invention are effective for error correctiontechnologies in the digital communication, and are particularly suitablefor a communication apparatus that decodes the LDPC encoded signal.

1-30. (canceled)
 31. A communication apparatus that iteratively decodesa codeword that has been encoded using low-density parity-check codingbased on a check matrix, the communication apparatus comprising: astorage unit that stores therein an intermediate value obtained by apredetermined process of a decoding algorithm; a first calculating unitthat performs row processing to calculate a first logarithmic likelihoodratio (LLR) used in column processing based on an absolute value of asecond LLR corresponding to a row weight of the check matrix, the firstLLR being sent from a check node to a bit node, and the second LLR beingsent from a bit node to a check node; and a second calculating unit thatperforms column processing to calculate a second LLR used in rowprocessing based on a first LLR corresponding to a column weight of thecheck matrix, and stores a minimum value of absolute values of thesecond LLR in the storage unit, wherein decoding is performed with thesecond calculating unit updating the minimum value.
 32. Thecommunication apparatus according to claim 31, wherein a row of thecheck matrix is divided into a predetermined number of subrows to obtaina divided matrix, the first calculating unit and the second calculatingunit perform the row processing and the column processing, respectively,in parallel on the divided matrix while sharing an area of the storageunit, and the second calculating unit updates the minimum value eachtime performing the column processing.
 33. The communication apparatusaccording to claim 31, wherein the first calculating unit multiplies aminimum value of absolute values of the second LLR corresponding to therow weight by a value obtained by multiplying signs of the second LLR toobtain a first LLR to be used in next column processing.
 34. Thecommunication apparatus according to claim 33, wherein the firstcalculating unit corrects the minimum value by a predeterminednormalization factor to obtain a corrected value, and obtains the firstLLR based on the corrected value.
 35. The communication apparatusaccording to claim 31, wherein the first calculating unit corrects aminimum value of absolute values of the second LLR corresponding to therow weight to an optimum value based on a predetermined correctionequation, and multiplies the optimum value by a value obtained bymultiplying signs of the second LLR to obtain a first LLR to be used innext column processing.
 36. The communication apparatus according toclaim 31, wherein the first calculating unit performs a predeterminedcalculation using table lookup on a minimum value of absolute values ofthe second LLR corresponding to the row weight to obtain a calculatedvalue, and multiplies the calculated value by a value obtained bymultiplying signs of the second LLR to obtain a first LLR to be used innext column processing.
 37. The communication apparatus according toclaim 33, wherein the first calculating unit multiplies signs of asecond LLR corresponding to a weight of a specific row, and at firstdecoding, the first calculating unit multiplies signs of a second LLRupdated by column processing of the first decoding for a column numbersmaller than a column number to be processed to obtain a firstmultiplied value, and multiplies signs of a second LLR updated by columnprocessing of (l−1)-th decoding for a column number larger than thecolumn number to be processed to obtain a second multiplied value, andmultiplies the first multiplied value and the second multiplied value.38. The communication apparatus according to claim 35, wherein the firstcalculating unit multiplies signs of a second LLR corresponding to aweight of a specific row, and at first decoding, the first calculatingunit multiplies signs of a second LLR updated by column processing ofthe first decoding for a column number smaller than a column number tobe processed to obtain a first multiplied value, and multiplies signs ofa second LLR updated by column processing of (l−1)-th decoding for acolumn number larger than the column number to be processed to obtain asecond multiplied value, and multiplies the first multiplied value andthe second multiplied value.
 39. The communication apparatus accordingto claim 36, wherein the first calculating unit multiplies signs of asecond LLR corresponding to a weight of a specific row, and at firstdecoding, the first calculating unit multiplies signs of a second LLRupdated by column processing of the first decoding for a column numbersmaller than a column number to be processed to obtain a firstmultiplied value, and multiplies signs of a second LLR updated by columnprocessing of (l−1)-th decoding for a column number larger than thecolumn number to be processed to obtain a second multiplied value, andmultiplies the first multiplied value and the second multiplied value.40. The communication apparatus according to claim 33, wherein the firstcalculating unit multiplies signs of a second LLR corresponding to aweight of a specific row, and at first decoding, the first calculatingunit multiplies a value obtained by multiplying signs of a second LLRcorresponding to a row weight updated by column processing of (l−1)-thdecoding by signs of a second LLR updated by column processing of the(l−1)-th decoding corresponding to a column number to be processed toobtain a multiplied value, and stores the multiplied value in thestorage unit.
 41. The communication apparatus according to claim 35,wherein the first calculating unit multiplies signs of a second LLRcorresponding to a weight of a specific row, and at first decoding, thefirst calculating unit multiplies a value obtained by multiplying signsof a second LLR corresponding to a row weight updated by columnprocessing of (l−1)-th decoding by signs of a second LLR updated bycolumn processing of the (l−1)-th decoding corresponding to a columnnumber to be processed to obtain a multiplied value, and stores themultiplied value in the storage unit.
 42. The communication apparatusaccording to claim 36, wherein the first calculating unit multipliessigns of a second LLR corresponding to a weight of a specific row, andat first decoding, the first calculating unit multiplies a valueobtained by multiplying signs of a second LLR corresponding to a rowweight updated by column processing of (l−1)-th decoding by signs of asecond LLR updated by column processing of the (l−1)-th decodingcorresponding to a column number to be processed to obtain a multipliedvalue, and stores the multiplied value in the storage unit.
 43. Thecommunication apparatus according to claim 40, wherein, at firstdecoding, the second calculating unit obtains the second LLR by adding areception LLR corresponding to the column number to be processed to asum of values of a first LLR corresponding to a column weight of a rownumber other than a number of a row to be processed, the secondcalculating unit updates the minimum value when an absolute value of thesecond LLR is smaller than at least one of minimum values of the row tobe processed, and the second calculating unit multiplies a sign of thesecond LLR by the multiplied value stored in the storage unit to updatethe multiplied value as a value obtained by multiplying signs of asecond LLR used in the (l−1)-th decoding.
 44. The communicationapparatus according to claim 41, wherein, at first decoding, the secondcalculating unit obtains the second LLR by adding a reception LLRcorresponding to the column number to be processed to a sum of values ofa first LLR corresponding to a column weight of a row number other thana number of a row to be processed, the second calculating unit updatesthe minimum value when an absolute value of the second LLR is smallerthan at least one of minimum values of the row to be processed, and thesecond calculating unit multiplies a sign of the second LLR by themultiplied value stored in the storage unit to update the multipliedvalue as a value obtained by multiplying signs of a second LLR used inthe (l−1)-th decoding.
 45. The communication apparatus according toclaim 42, wherein, at first decoding, the second calculating unitobtains the second LLR by adding a reception LLR corresponding to thecolumn number to be processed to a sum of values of a first LLRcorresponding to a column weight of a row number other than a number ofa row to be processed, the second calculating unit updates the minimumvalue when an absolute value of the second LLR is smaller than at leastone of minimum values of the row to be processed, and the secondcalculating unit multiplies a sign of the second LLR by the multipliedvalue stored in the storage unit to update the multiplied value as avalue obtained by multiplying signs of a second LLR used in the (l−1)-thdecoding.
 46. The communication apparatus according to claim 31, whereinthe first calculating unit uses a minimum value of absolute values of areception LLR as the minimum value at first decoding.
 47. Thecommunication apparatus according to claim 31, wherein the secondcalculating unit calculates a posterior value each time performing thecolumn processing, makes a hard decision on the posterior value, andoutputs a result of the hard decision as a decoding result when a paritycheck is successful or a predetermined maximum number of iterations hasbeen reached.
 48. The communication apparatus according to claim 31,wherein a starting column for the row processing is arbitrary, anditerative decoding is performed from the starting column again whenprocessing is completed to the last column.
 49. The communicationapparatus according to claim 31, wherein a starting column for the rowprocessing is arbitrary, and processing is performed on arbitrarycolumns not overlapped in a specific order, and upon completion of theprocessing for all columns, iterative decoding is performed on thecolumns in the specific order.
 50. The communication apparatus accordingto claim 31, wherein a starting column for the row processing isarbitrary, and processing is performed on arbitrary columns notoverlapped in a first order, and upon completion of the processing forall columns, iterative decoding is performed on the arbitrary columns ina second order until completion of the iterative decoding of allcolumns.
 51. The communication apparatus according to claim 31, whereina column number of the row weight of the check matrix is indicated in anascending order from a small column number.
 52. A communicationapparatus that iteratively decodes a codeword that has been encodedusing low-density parity-check coding based on a check matrix, thecommunication apparatus comprising: a first calculating unit thatperforms row processing to calculate a first logarithmic likelihoodratio (LLR) used in column processing based on an absolute value of asecond LLR corresponding to a row weight of the check matrix, the firstLLR being sent from a check node to a bit node, and the second LLR beingsent from a bit node to a check node; and a second calculating unit thatperforms column processing to calculate a second LLR used in rowprocessing based on a first LLR corresponding to a column weight of thecheck matrix, wherein the first calculating unit and the secondcalculating unit alternately perform the row processing and the columnprocessing a predetermined number of times, and cyclically update thefirst LLR and the second LLR.
 53. The communication apparatus accordingto claim 52, wherein the first calculating unit multiplies a minimumvalue of absolute values of the second LLR corresponding to the rowweight by a value obtained by multiplying signs of the second LLR toobtain a first LLR to be used in next column processing.
 54. Thecommunication apparatus according to claim 53, wherein the firstcalculating unit corrects the minimum value by a predeterminednormalization factor to obtain a corrected value, and obtains the firstLLR based on the corrected value.
 55. The communication apparatusaccording to claim 52, wherein the first calculating unit corrects aminimum value of absolute values of the second LLR corresponding to therow weight to an optimum value based on a predetermined correctionequation, and multiplies the optimum value by a value obtained bymultiplying signs of the second LLR to obtain a first LLR to be used innext column processing.
 56. The communication apparatus according toclaim 52, wherein the first calculating unit performs a predeterminedcalculation using table lookup on a minimum value of absolute values ofthe second LLR corresponding to the row weight to obtain a calculatedvalue, and multiplies the calculated value by a value obtained bymultiplying signs of the second LLR to obtain a first LLR to be used innext column processing.
 57. The communication apparatus according toclaim 52, wherein the first calculating unit multiplies signs of asecond LLR corresponding to a weight of a specific row, and at firstdecoding, the first calculating unit multiplies signs of a second LLRupdated by column processing of the first decoding for a column numbersmaller than a column number to be processed to obtain a firstmultiplied value, and multiplies signs of a second LLR updated by columnprocessing of (l−1)-th decoding for a column number larger than thecolumn number to be processed to obtain a second multiplied value, andmultiplies the first multiplied value and the second multiplied value.58. The communication apparatus according to claim 52, wherein the firstcalculating unit uses a minimum value of absolute values of a receptionLLR as the minimum value at first decoding.
 59. The communicationapparatus according to claim 52, wherein the second calculating unitcalculates a posterior value each time performing the column processing,makes a hard decision on the posterior value, and outputs a result ofthe hard decision as a decoding result when a parity check is successfulor a predetermined maximum number of iterations has been reached. 60.The communication apparatus according to claim 52, wherein a startingcolumn for the row processing is arbitrary, and iterative decoding isperformed from the starting column again when processing is completed tothe last column.
 61. The communication apparatus according to claim 52,wherein a starting column for the row processing is arbitrary, andprocessing is performed on arbitrary columns not overlapped in aspecific order, and upon completion of the processing for all columns,iterative decoding is performed on the columns in the specific order.62. The communication apparatus according to claim 52, wherein astarting column for the row processing is arbitrary, and processing isperformed on arbitrary columns not overlapped in a first order, and uponcompletion of the processing for all columns, iterative decoding isperformed on the arbitrary columns in a second order until completion ofthe iterative decoding of all columns.
 63. The communication apparatusaccording to claim 52, wherein a column number of the row weight of thecheck matrix is indicated in an ascending order from a small columnnumber.
 64. The communication apparatus according to claim 52, whereinthe first calculating unit and the second calculating unit update thefirst LLR and the second LLR each time performing the row processing andthe column processing.
 65. A decoding method for iteratively decoding acodeword that has been encoded using low-density parity-check codingbased on a check matrix, the decoding method comprising: firstcalculating by row processing a first logarithmic likelihood ratio (LLR)used in column processing based on an absolute value of a second LLRcorresponding to a row weight of the check matrix, the first LLR beingsent from a check node to a bit node, and the second LLR being sent froma bit node to a check node; second calculating by column processing asecond LLR used in row processing based on a first LLR corresponding toa column weight of the check matrix obtained by the row processing;storing a minimum value of absolute values of the second LLR in apredetermined area of a memory; and performing decoding while updatingthe minimum value.
 66. A decoding method for iteratively decoding acodeword that has been encoded using low-density parity-check codingbased on a check matrix, the decoding method comprising: firstcalculating by row processing a first logarithmic likelihood ratio (LLR)used in column processing based on an absolute value of a second LLRcorresponding to a row weight of the check matrix, the first LLR beingsent from a check node to a bit node, and the second LLR being sent froma bit node to a check node; second calculating by column processing asecond LLR used in row processing based on a first LLR corresponding toa column weight of the check matrix obtained by the row processing;alternately perform the row processing and the column processing apredetermined number of times to cyclically update the first LLR and thesecond LLR.